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74F114 Datasheet(PDF) 1 Page - NXP Semiconductors

No. de pieza 74F114
Descripción Electrónicos  Dual J-K negative edge-triggered flip-flop with common clock and reset
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Fabricante Electrónico  PHILIPS [NXP Semiconductors]
Página de inicio  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74F114 Datasheet(HTML) 1 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74F114
Dual J-K negative edge-triggered flip-flop
with common clock and reset
1
1996 Mar 14
853–0340 16572
DESCRIPTION
The 74F114, Dual Negative edge-triggered JK-Type Flip-Flop with
common clock and reset inputs, features individual J, K, Clock (CP),
Set (SD) and Reset (RD) inputs, true and complementary outputs.
The SD and RD inputs, when Low, set or reset the outputs as shown
in the Function Table regardless of the level at the other inputs.
A High level on the clock (CP) input enables the J and K inputs and
data will be accepted. The logic levels and data will be accepted.
The logic levels at the J and K inputs may be allowed to change
while the CP is High and flip-flop will perform according to the
Function Table as long as minimum setup and hold times are
observed. Output changes are initiated by the High-to-Low transition
of the CP.
TYPE
TYPICAL fMAX
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F114
100MHz
15mA
PIN CONFIGURATION
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
VCC
SD1
Q1
Q1
J1
CP
K1
RD
K0
Q0
J0
SD0
Q0
SF00110
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
PKG. DWG. #
14-pin plastic DIP
N74F114N
SOT27-1
14-pin plastic SO
N74F114D
SOT108-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
LOAD VALUE HIGH/LOW
J0, J1
J inputs
1.0/1.0
20
µA/0.6mA
K0, K1
K inputs
1.0/1.0
20
µA/0.6mA
SD0, SD1
Set inputs (active Low)
1.0/5.0
20
µA/3.0mA
RD
Reset input (active Low)
1.0/10.0
20
µA/6.0mA
CP
Clock Pulse input (active falling edge)
1.0/8.0
20
µA/4.8mA
Q0, Q0; Q1, Q1
Data outputs
50/33
1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20
µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
Q0
Q0
Q1
Q1
56
98
VCC = Pin 14
GND = Pin 7
13
4
1
10
CP
SD0
RD0
SD1
J1
K0
212
SF00111
K1
J0
311
IEC/IEEE SYMBOL
SF00112
4
3
2
9
8
S
1K
1J
1
R
13
C1
10
11
12
5
6


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