Si5319

Preliminary Rev. 0.3

7

2. Pin Descriptions: Si5319

Pin numbers are preliminary and subject to change.

Pin #

Pin Name

I/O

Signal Level

Description

1

RST

ILVCMOS

External Reset.

Active low input that performs external hardware reset of device.

Resets all internal logic to a known state and forces the device regis-

ters to their default value. Clock outputs are disabled during reset. The

part must be programmed after a reset or power-on to get a clock out-

put. See Family Reference Manual for details.

This pin has a weak pull-up.

2, 4, 9,

12–14,

30,

33–35

NC

—

—

No Connect.

This pin must be left unconnected for normal operation.

3INT_CB

O

LVCMOS

Interrupt/CKIN Invalid Indicator.

This pin functions as a device interrupt output or an alarm output for

CKIN. If used as an interrupt output, INT_PIN must be set to 1. The pin

functions as a maskable interrupt output with active polarity controlled

by the INT_POL register bit.

If used as an alarm output, the pin functions as a LOS alarm indicator

for CKIN. Set CK_BAD_PIN = 1 and INT_PIN =0.

0 = CKIN present.

1 = LOS on CKIN.

The active polarity is controlled by CK_BAD_POL. If no function is

selected, the pin tristates.

Note: Internal register names are indicated by underlined italics (e.g., INT_PIN. See Si5319 Register Map).

1

2

3

29

30

31

32

33

34

35

36

20

21

22

23

24

25

26

27

10 11 12 13 14 15 16 17

4

5

6

7

8

NC

NC

RST

NC

INT_CB

GND

VDD

XA

CS

SCL

SDA_SDO

A1

A2_SS

SDI

GND

Pad

A0

GND

9

18

19

28

XB

GND