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CAT93HC46UETE13 Datasheet(PDF) 4 Page - Catalyst Semiconductor |
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CAT93HC46UETE13 Datasheet(HTML) 4 Page - Catalyst Semiconductor |
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4 / 9 page  Discontinued Part 4 CAT93HC46 Doc. No. 1008, Rev. H DEVICE OPERATION The CAT93HC46 is a 1024-bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93HC46 can be organized as registers of either 16 bits or 8 bits. When organized as X16, seven 9-bit instructions control the reading, writing and erase operations of the device. When organized as X8, seven 10-bit instructions control the operation of the device. The CAT93HC46 operates on a single power supply and will generate on chip the high voltage required during write operation. Instructions, addresses, and data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state, except when reading data from the device, or when checking the ready/busy status after a write operation. The ready/busy status can be determined after the start of a write operation by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state by shifting a dummy “1” into the DI pin. The DO pin will enter the high impedance state on the falling edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin. The format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit byte/ word address (an additional bit when organized X8) and for write operations a 16-bit data field (8-bit for X8 organization). Figure 1. Sychronous Data Timing SK DI CS DO tDIS tPD0,tPD1 tCSMIN tCSS tDIS tDIH tSKHI tCSH VALID VALID DATA VALID tSKLOW INSTRUCTION SET Start Address Data Instruction Bit Opcode x8 x16 x8 x16 Comments READ 1 10 A6-A0 A5-A0 Read Address AN–A0 ERASE 1 11 A6-A0 A5-A0 Clear Address AN–A0 WRITE 1 01 A6-A0 A5-A0 D7-D0 D15-D0 Write Address AN–A0 EWEN 1 00 11XXXXX 11XXXX Write Enable EWDS 1 00 00XXXXX 00XXXX Write Disable ERAL 1 00 10XXXXX 10XXXX Clear All Addresses WRAL 1 00 01XXXXX 01XXXX D7-D0 D15-D0 Write All Addresses |
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