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M27V402-150B5TR Datasheet(PDF) 5 Page - STMicroelectronics |
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M27V402-150B5TR Datasheet(HTML) 5 Page - STMicroelectronics |
5 / 15 page 5/15 M27V402 Table 7. Read Mode DC Characteristics (1) (TA = 0 to 70 °C, –20 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3.3V ± 10%; VPP =VCC) Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Maximum DC voltage on Output is VCC +0.5V. Symbol Parameter Test Condition Min Max Unit ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±10 µA ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±10 µA ICC Supply Current E=VIL,G= VIL,IOUT = 0mA, f = 5MHz, VCC = 3.6V 20 mA ICC1 Supply Current (Standby) TTL E= VIH 1mA ICC2 Supply Current (Standby) CMOS E> VCC – 0.2V, VCC = 3.6V 20 µA IPP Program Current VPP =VCC 10 µA VIL Input Low Voltage –0.3 0.8 V VIH (2) Input High Voltage 2 VCC +1 V VOL Output Low Voltage IOL = 2.1mA 0.4 V VOH Output High Voltage TTL IOH = –400µA 2.4 V Output High Voltage CMOS IOH = –100µAVCC–0.7V V System Considerations The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices. The supply current, ICC, has three seg- ments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of the transient current peaks is dependent on the output capacitive and inductive loading of the de- vice. The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling ca- pacitors. It is recommended that a 0.1 µF ceramic capacitor be used on every device between VCC and VSS. This should be a high frequency capaci- tor of low inherent inductance and should be placed as close to the device as possible. In addi- tion, a 4.7 µF bulk electrolytic capacitor should be used between VCC and VSS for every eight devic- es. The bulk capacitor should be located near the power supply connection point.The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces. Programming When delivered (and after each erasure for UV EPROM), all bits of the M27V402 are in the ’1’ state. Data is introduced by selectively program- ming ’0’s into the desired bit locations. Although only ’0’s will be programmed, both ’1’s and ’0’s can be present in the data word. The only way to change a ’0’ to a ’1’ is by die exposure to ultraviolet light (UV EPROM). The M27V402 is in the pro- gramming mode when VPP input is at 12.75V, G ia at VIH and E is pulsed to VIL. The data to be pro- grammed is applied to 16 bits in parallel to the data output pins. The levels required for the address and data in- puts are TTL. VCC is specified to be 6.25V ± 0.25V. |
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