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CAP3001A Datasheet(PDF) 8 Page - Micronas

No. de pieza CAP3001A
Descripción Electrónicos  Car Audio Processor Hardware
Download  37 Pages
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Fabricante Electrónico  MICRONAS [Micronas]
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CAP3001A Datasheet(HTML) 8 Page - Micronas

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CAP 3001 A
2.1.7. Stereo Mixer AMIX
This analog demodulator mixes the incoming multiplex
signal with the PLL-synchronized 38 kHz subcarrier in
order to get the difference channel in baseband.
The phase of the mixer signal is locked to the phase of
the digital pilot demodulator; the phase shift between the
two signals has to be compensated by the signal proces-
sor’s Stereo PLL software.
The realized modulator consists of an analog multiplex-
er switching among the original input signal, the inverted
input signal and zero input.
Fig. 2–4: Difference channel mixing signal
The desired fundamental 38 kHz component includes
an additional factor of 1.10266 which has to be taken into
account in the dematrix-software of the signal proces-
2.1.8. AM Mixer AMMIX
This analog modulator mixes the incoming AM-IF signal
down to approximately 19 kHz. Just like the AMIX stereo
mixer it uses an amplitude discrete signal instead of a si-
nusoidal signal.
The realized modulator consists of an analog multiplex-
er switching among the original input signal and the in-
verted input signal. The mixing frequency of this mixer
is typically between 430 and 440 kHz and can be se-
lected in approximately 2 kHz steps in order to choose
the desired AM IF frequency.
2.1.9. Multiplexers AMUX
The analog multiplexers allow the selection of one of the
input signals for each signal path.
2.1.10. A/D-Converters ADC
The A/D-converters are realized as pulse density modu-
lators (PDMs) running at a clock frequency of
+8.208 MHz. The ADC0, ADC1 and the ADC2 are
high quality double-loop PDMs with one external capaci-
tor whereas ADC3 and ADC4 are low quality PDMs with-
out any external capacitor.
2.1.11. Digital Signal Processing Block
2.1.12. Digital Filter Sections
After analog to digital conversion, the input signals are
filtered by means of digital filters in order to decimate the
high frequency PDM signals to an appropriate sampling
rate. The second purpose of these filters is to suppress
unwanted out-of-band signals and to shape the input
signals to the desired response. After being processed
in the DSP section, the digital samples are interpolated
to a higher rate before being converted to the analog do-
main. The individual filter blocks can be seen in Fig. 2–5
and 2–6. Fig. 2–5 shows filter sections for the A/D side
whereas in Fig. 2–6, filter blocks for the interpolation pro-
cess on the D/A side can be seen. In the text of the CAP
3001 A data sheet, the filter blocks are referred to with
the names indicated in the schematics.
Most of the filters are designed as multirate FIR blocks.
Fig. 2–7 shows the overall (A/D to D/A) passband char-
acteristics of the main channels in TAPE or AUX mode.
The shown 3 dB bandwidth is more than 18 kHz. Fig. 2–8
shows the same for the MPX case. An additional pilot
notch filter (19 kHz) suppresses higher frequencies. In
case of a locked stereo PLL, the suppression is ideal.
Fig. 2–9 depicts the characteristics of the ARI/RDS
bandpass. The near-by difference channel is attenuated
sufficiently in order to minimize disturbing effects in the
weak ARI/RDS signal. An additional lowpass with roll-off
characteristics is done in the DSP software.
In order to suppress out-of-band signals, the CAP
3001 A is equipped with digital interpolation filters.
These filters attenuate alias frequencies of up to eight
times the sampling frequency by at least 50 dB. The in-
terpolation block consists of three cascaded linear
phase FIR filters. A simple sample and hold filter serves
for the interpolation to the operating rate of the D/A con-
verter. The overall interpolation rate is therefore 32. See
Fig. 2–10 for the passband characteristics of the inter-
polation filter (plotted for 44.1 kHz sampling rate) and
Fig. 2–11 for the stopband characteristics.

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