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ADSP-BF539BBCZ-5F8 Datasheet(PDF) 7 Page - Analog Devices |
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ADSP-BF539BBCZ-5F8 Datasheet(HTML) 7 Page - Analog Devices |
7 / 60 page ADSP-BF539/ADSP-BF539F Rev. A | Page 7 of 60 | February 2008 Booting The ADSP-BF539/ADSP-BF539F processor contains a small boot kernel, which configures the appropriate peripheral for booting. If the ADSP-BF539/ADSP-BF539F processor is config- ured to boot from boot ROM memory space, the processor starts executing from the on-chip boot ROM. For more infor- mation, see Booting Modes on Page 16. Event Handling The event controller on the ADSP-BF539/ADSP-BF539F pro- cessor handles all asynchronous and synchronous events to the processor. The ADSP-BF539/ADSP-BF539F processor provides event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higher priority event takes precedence over servicing of a lower priority event. The controller provides support for five different types of events: • Emulation – An emulation event causes the processor to enter emulation mode, allowing command and control of the processor via the JTAG interface. • Reset – This event resets the processor. • Nonmaskable Interrupt (NMI) – The NMI event can be generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shut- down of the system. • Exceptions – Events that occur synchronously to program flow (i.e., the exception will be taken before the instruction is allowed to complete). Conditions such as data alignment violations and undefined instructions cause exceptions. • Interrupts – Events that occur asynchronously to program flow. They are caused by input pins, timers, and other peripherals, as well as by an explicit software instruction. Each event type has an associated register to hold the return address and an associated return-from-event instruction. When an event is triggered, the state of the processor is saved on the supervisor stack. The ADSP-BF539/ADSP-BF539F processor’s event controller consists of two stages, the core event controller (CEC) and the system interrupt controllers (SIC). The core event controller works with the system interrupt controllers to prioritize and control all system events. Conceptually, interrupts from the peripherals enter into one of the SIC, and are then routed directly into the general-purpose interrupts of the CEC. Core Event Controller (CEC) The CEC supports nine general-purpose interrupts (IVG15–7), in addition to the dedicated interrupt and exception events. Of these general-purpose interrupts, the two lowest priority inter- rupts (IVG15–14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the ADSP-BF539/ADSP-BF539F pro- cessors. Table 2 describes the inputs to the CEC, identifies their names in the event vector table (EVT), and lists their priorities. System Interrupt Controllers (SIC) The system interrupt controllers (SIC0, SIC1) provide the map- ping and routing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the CEC. Although the ADSP-BF539/ADSP-BF539F processors provide a default mapping, the user can alter the mappings and priorities of interrupt events by writing the appropriate values into the interrupt assignment registers (SIC_IARx). Table 3 describes the inputs into the SICs and the default mappings into the CEC. Table 2. Core Event Controller (CEC) Priority (0 is Highest) Event Class EVT Entry 0 Emulation/Test Control EMU 1 Reset RST 2 Nonmaskable Interrupt NMI 3Exception EVX 4 Reserved — 5 Hardware Error IVHW 6 Core Timer IVTMR 7 General Interrupt 7 IVG7 8 General Interrupt 8 IVG8 9 General Interrupt 9 IVG9 10 General Interrupt 10 IVG10 11 General Interrupt 11 IVG11 12 General Interrupt 12 IVG12 13 General Interrupt 13 IVG13 14 General Interrupt 14 IVG14 15 General Interrupt 15 IVG15 Table 3. System and Core Event Mapping Event Source Core Event Name PLL Wake-up Interrupt IVG7 DMA Controller 0 Error IVG7 DMA Controller 1 Error IVG7 PPI Error Interrupt IVG7 SPORT0 Error Interrupt IVG7 SPORT1 Error Interrupt IVG7 SPORT2 Error Interrupt IVG7 SPORT3 Error Interrupt IVG7 MXVR Synchronous Data Interrupt IVG7 SPI0 Error Interrupt IVG7 SPI1 Error Interrupt IVG7 SPI2 Error Interrupt IVG7 UART0 Error Interrupt IVG7 UART1 Error Interrupt IVG7 |
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