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UPA to PCI Interface
U2P
STP2223BGA
July 1997
UPA_A[8]
B10
IO
BN02Z24S
UPA address
UPA_A[11]
B11
IO
BN02Z24S
UPA address
UPA_A[15]
B12
IO
BN02Z24S
UPA address
UPA_A[20]
B13
IO
BN02Z24S
UPA address
UPA_A[23]
B14
IO
BN02Z24S
UPA address
UPA_A[28]
B15
IO
BN02Z24S
UPA address
UPA_A[32]
B16
IO
BN02Z24S
UPA address
UPA_RST_L
B17
I
PINX02S
UPA reset. Main U2P reset.
INT_NUM[3]
B18
I
B5IN03S
Interrupt number
EXT_EVENT
B19
IO
PNAXZ24S
External event interrupt
INT_EVENT
B20
O
BOZ24S
Internal event interrupt
UPA_CLK
B21
I
BIED03S
UPA 100MHz input clock (pos, PECL)
UPA_BYPASS
B22
I
BIN06NA
UPA PLL bypass
PSYCLOPS_CLK
B23
I
BIN02NA
66MHz main clock
A_AD[1]
B24
IO
PCIMXI21
PCIA address/data bus
A_AD[3]
B25
IO
PCIMXI21
PCIA address/data bus
VSS
B26
UPA_ECC[4]
C1
IO
BN02Z24S
UPA ECC bus
UPA_ECC[3]
C2
IO
BN02Z24S
UPA ECC bus
UPA_ECC[7]
C3
IO
BN02Z24S
UPA ECC bus
UPA_SRLY[1]
C4
I
BIN02S
UPA system reply
UPA_DTST
C5
I
BIN02S
UPA data stall
UPA_PRLY[2]
C6
O
BOZ24S
UPA port reply
UPA_ARBRST_L
C7
I
BIN02S
UPA arbitration reset
UPA_RIN[2]
C8
I
BIN02S
UPA request in
UPA_A[2]
C9
IO
BN02Z24S
UPA address
UPA_A[6]
C10
IO
BN02Z24S
UPA address
UPA_A[10]
C11
IO
BN02Z24S
UPA address
UPA_A[13]
C12
IO
BN02Z24S
UPA address
UPA_A[18]
C13
IO
BN02Z24S
UPA address
UPA_A[25]
C14
IO
BN02Z24S
UPA address
UPA_A[30]
C15
IO
BN02Z24S
UPA address
UPA_A[33]
C16
IO
BN02Z24S
UPA address
INT_NUM[1]
C17
I
B5IN03S
Interrupt number
INT_NUM[5]
C18
I
B5IN03S
Interrupt number
PSY_TMS
C19
I
PINA02S
JTAG Test mode select
VDDA-VA1
C20
NVDDAN
PLL 3.3V supply, filtered
TABLE 3: PBGA Pinout (Continued)
Signal Name
Ball
Direction
Cell Type
Description
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