Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 376
Figure 15-13. Slave Command Sequence ............................................................................................ 377
Figure 16-1.
CAN Module Block Diagram ........................................................................................... 402
Figure 16-2.
CAN Bit Time ................................................................................................................ 409
Figure 17-1.
Analog Comparator Module Block Diagram ..................................................................... 446
Figure 17-2.
Structure of Comparator Unit .......................................................................................... 447
Figure 17-3.
Comparator Internal Reference Structure ........................................................................ 448
Figure 18-1.
PWM Module Block Diagram .......................................................................................... 458
Figure 18-2.
PWM Count-Down Mode ................................................................................................ 459
Figure 18-3.
PWM Count-Up/Down Mode .......................................................................................... 460
Figure 18-4.
PWM Generation Example In Count-Up/Down Mode ....................................................... 460
Figure 18-5.
PWM Dead-Band Generator ........................................................................................... 461
Figure 19-1.
QEI Block Diagram ........................................................................................................ 490
Figure 19-2.
Quadrature Encoder and Velocity Predivider Operation .................................................... 491
Figure 20-1.
Pin Connection Diagram ................................................................................................ 506
Figure 23-1.
Load Conditions ............................................................................................................ 526
Figure 23-2.
I
2C Timing ..................................................................................................................... 529
Figure 23-3.
Hibernation Module Timing ............................................................................................. 529
Figure 23-4.
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 530
Figure 23-5.
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 530
Figure 23-6.
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 531
Figure 23-7.
JTAG Test Clock Input Timing ......................................................................................... 532
Figure 23-8.
JTAG Test Access Port (TAP) Timing .............................................................................. 532
Figure 23-9.
JTAG TRST Timing ........................................................................................................ 532
Figure 23-10. External Reset Timing (RST) ........................................................................................... 533
Figure 23-11. Power-On Reset Timing ................................................................................................. 534
Figure 23-12. Brown-Out Reset Timing ................................................................................................ 534
Figure 23-13. Software Reset Timing ................................................................................................... 534
Figure 23-14. Watchdog Reset Timing ................................................................................................. 534
Figure 24-1.
100-Pin LQFP Package .................................................................................................. 535
June 04, 2007
10
Preliminary
Table of Contents