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SST89E54RD2-40-I-TQI Datasheet(PDF) 74 Page - Silicon Storage Technology, Inc |
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SST89E54RD2-40-I-TQI Datasheet(HTML) 74 Page - Silicon Storage Technology, Inc |
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74 / 81 page  74 Data Sheet FlashFlex51 MCU SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD ©2006 Silicon Storage Technology, Inc. S71255-05-000 5/06 FIGURE 14-7: Shift Register Mode Timing Waveforms FIGURE 14-8: AC Testing Input/Output Test Waveform FIGURE 14-9: Float Waveform TABLE 14-10: Serial Port Timing Symbol Parameter Oscillator Units 12MHz 40MHz Variable Min Max Min Max Min Max TXLXL Serial Port Clock Cycle Time 1.0 0.3 12TCLCL µs TQVXH Output Data Setup to Clock Rising Edge 700 117 10TCLCL - 133 ns TXHQX Output Data Hold After Clock Rising Edge 50 2TCLCL - 117 ns 02TCLCL - 50 ns TXHDX Input Data Hold After Clock Rising Edge 0 0 0 ns TXHDV Clock Rising Edge to Input Data Valid 700 117 10TCLCL - 133 ns T14-10.0 1255 1255 F39.0 ALE 0 INSTRUCTION CLOCK OUTPUT DATA WRITE TO SBUF VALID VALID VALID VALID VALID VALID VALID VALID INPUT DATA CLEAR RI 01 2 3 4 5 6 7 TXLXL TQVXH TXHQX TXHDV TXHDX SET TI SET R I 1 2 3 4 5 6 7 8 VLT AC Inputs during testing are driven at VIHT (VDD -0.5V) for Logic "1" and VILT (0.45V) for a Logic "0". Measurement reference points for inputs and outputs are at VHT (0.2VDD + 0.9) and VLT (0.2VDD - 0.1) VHT VIHT VILT 1255 F40.0 Note: VHT- VHIGH Test VLT- VLOW Test VIHT-VINPUT HIGH Test VILT- VINPUT LOW Test For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs, and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH = ± 20mA. VLOAD +0.1V VLOAD -0.1V VOH -0.1V Timing Reference Points VOL +0.1V VLOAD 1255 F41.0 |
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