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SST89V52RD2-33-C-TQJ Datasheet(PDF) 45 Page - Silicon Storage Technology, Inc |
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SST89V52RD2-33-C-TQJ Datasheet(HTML) 45 Page - Silicon Storage Technology, Inc |
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45 / 81 page  Data Sheet FlashFlex51 MCU SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD 45 ©2006 Silicon Storage Technology, Inc. S71255-05-000 5/06 7.0 WATCHDOG TIMER The device offers a programmable Watchdog Timer (WDT) for fail safe protection against software deadlock and auto- matic recovery. To protect the system against software deadlock, the user software must refresh the WDT within a user-defined time period. If the software fails to do this periodical refresh, an internal hardware reset will be initiated if enabled (WDRE= 1). The software can be designed such that the WDT times out if the program does not work properly. The WDT in the device uses the system clock (XTAL1) as its time base. So strictly speaking, it is a watchdog counter rather than a watchdog timer. The WDT register will incre- ment every 344,064 crystal clocks. The upper 8-bits of the time base register (WDTD) are used as the reload register of the WDT. The WDTS flag bit is set by WDT overflow and is not changed by WDT reset. User software can clear WDTS by writing “1” to it. Figure 7-1 provides a block diagram of the WDT. Two SFRs (WDTC and WDTD) control watchdog timer operation. During idle mode, WDT operation is temporarily sus- pended, and resumes upon an interrupt exit from idle. The time-out period of the WDT is calculated as follows: Period = (255 - WDTD) * 344064 * 1/fCLK (XTAL1) where WDTD is the value loaded into the WDTD register and fOSC is the oscillator frequency. FIGURE 7-1: Block Diagram of Programmable Watchdog Timer 1255 F22.0 WDT Upper Byte WDT Reset Internal Reset 344064 clks Counter CLK (XTAL1) Ext. RST WDTC WDTD |
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