LM2507SQ datasheet(2/22 Pages) NSC

No. de pieza	LM2507SQ

Descripción Electrónicos	Low Power Mobile Pixel Link (MPL) Level 0, 16-bit CPU Display interface Serializer and Deserializer

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Fabricante Electrónico	NSC [National Semiconductor (TI)]

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Pin Descriptions — CPU

Pin Name

No.

of Pins

I/O, Type

Description

CPU Master

(MST)

CPU Slave

(SLV)

MPL SERIAL BUS PINS

MD[1:0]

2

IO, MPL

MPL Data Line Driver/Receiver

MPL Data Receiver/Line Driver

MC

1

IO, MPL

MPL Clock Line Driver

MPL Clock Receiver

V

SSA

Ground

MPL Ground - see Power/Ground Pins

CONFIGURATION/PARALLEL BUS PINS

CPU

1

I,

LVCMOS

CPU mode configuration input

Tie High

M/S*

1

I,

LVCMOS

Tie High for Master

Tie Low for Slave

TM

1

I,

LVCMOS

Test Mode control input

Tie Low for normal mode (High reserved for factory test)

Mode

1

I,

LVCMOS

CPU Mode input

Tie High for i80 mode

CSL*/IDR

1

I,

LVCMOS

Local Chip Select input,

Reserved - Tie High.

Insert Dummy Read control input,

H = inserts dummy read cycle in all

READ transactions

L = uses one READ cycle for every

READ transaction

CLOCK / POWER DOWN SIGNALS

CLK

1

I,

LVCMOS

CLK input

NA

PD*

1

I,

LVCMOS

Power Down input,

L = Powered down (sleep mode)

H = active mode

PARALLEL INTERFACE SIGNALS

D[15:0]

16

IO,

LVCMOS

CPU Data Bus inputs / outputs

CPU Data Bus outputs / inputs

MF0

(RD*)

1

IO,

LVCMOS

Multi Function input -

Read input (RD*) for i80 I/F

Multi Function output -

Read output (RD*) for i80 I/F

MF1

(WR*)

1

IO,

LVCMOS

Multi Function input -

Write input (WR*) for i80 I/F

Multi Function output -

Write output (WR*) for i80 I/F

CS1*

1

IO,

LVCMOS

Chip Select One input

Active Low

Chip Select One output

Active Low

CS2*

1

IO,

LVCMOS

Chip Select Two input

Active Low

Chip Select Two output

Active Low

A/D

1

IO,

LVCMOS

Address / Data selector input

Address / Data selector output

INTR/8-bit

1

IO,

LVCMOS

Interrupt Output

Active High, is asserted when READ

data is ready and de-asserted upon send

READ cycle OPTIONAL

8-bit Mode Input

Tie Low for 16-bit mode

8-bit mode is reserved.

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LM2507SQ Datasheet(PDF) 2 Page - National Semiconductor (TI)

LM2507SQ Datasheet(HTML) 2 Page - National Semiconductor (TI)

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