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LC128646-NFLNS3V Datasheet(Hoja de datos) 7 Page - List of Unclassifed Manufacturers

No. de Pieza. LC128646-NFLNS3V
Descripción  LCD Module Specification
Descarga  20 Pages
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Fabricante  ETC2 [List of Unclassifed Manufacturers]
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LG128642-BMDWH6V
- 7 -
4. OPERATING PRINCIPLES & METHODES
4.1 I/O Buffer
Input buffer controls the status between the enable and display of chip. Unless the IC
(selected by /CS1, /CS2) is in active mode, input or output of data and instruction does
not execute. Therefore internal state is maintained. But /RST can operate regardless the
level of /CS1 or /CS2.
4.2 Register
Both input register and output register are provided to interface to MPU of which the
speed is different from that of internal operation. The selections of these registers depend
on the combination of R/W and RS signals.
RS
R/W
Function
L
Instruction
L
H
Status read (busy check)
L
Data write (from input register to display data RAM)
H
H
Data read (from display data RAM to output register)
4.2.1 Input Register
Input register stores the data temporarily before writing it into display data RAM.
When the IC is in active mode, R/W and RS select the input register. The data from MPU
is written into input register, then into display data RAM. Data is latched at falling edge of
the E signal and then written into the display data RAM automatically by internal
operation.
4.2.2 Output Register
Output register stores the data temporarily which is read from display data RAM when the
IC is in active mode and R/W and RS=H, stored data in display data RAM is latched in
output register. When the IC is in active mode and R/W=H, RS=L, status data (busy
check) can be read out.
To read the contents of display data RAM, twice access of read instruction is needed. In
first access, data in display data RAM is latched into output register. In second access,
MPU can read data that is latched in output register. That is, to read the data in display
data RAM, it needs dummy read. But status read does not need dummy read.
The following shows the MPU read timing.




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