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ADS5545 Datasheet(PDF) 7 Page - Texas Instruments |
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ADS5545 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 54 page www.ti.com DIGITAL CHARACTERISTICS (1) TIMING CHARACTERISTICS – LVDS AND CMOS MODES (1) ADS5517 SLWS203 – DECEMBER 2007 The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1 AVDD = DRVDD = 3.3 V, IO = 3.5 mA, RL = 100 Ω (2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS High-level input voltage 2.4 V Low-level input voltage 0.8 V High-level input current 33 µA Low-level input current –33 µA Input capacitance 4 pF DIGITAL OUTPUTS – CMOS MODE High-level output voltage 3.3 V Low-level output voltage 0 V Output capacitance Output capacitance inside the device, from each output to 2 pF ground DIGITAL OUTPUTS – LVDS MODE High-level output voltage 1375 mV Low-level output voltage 1025 mV Output differential voltage, |VOD| 225 350 425 mV VOS Output offset voltage, single-ended Common-mode voltage of OUTP and OUTM 1200 mV Output capacitance inside the device, from either output to Output capacitance 2 pF ground (1) All LVDS and CMOS specifications are characterized, but not tested at production. (2) IO refers to the LVDS buffer current setting, RL is the differential load resistance between the LVDS output pair. Typical values are at 25 °C, min and max values are across the full temperature range T MIN = –40°C to TMAX = 85°C, AVDD = DRVDD = 3.3 V, sampling frequency = 200 MSPS, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), I O = 3.5 mA, RL = 100 Ω (3), no internal termination, unless otherwise noted. For timings at lower sampling frequencies, see the Output Timing section in the APPLICATION INFORMATION of this data sheet. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ta Aperture delay 1.2 ns tj Aperture jitter 150 fs rms Time to valid data after coming out of 100 STANDBY mode Wake-up time µs Time to valid data after stopping and 100 restarting the input clock clock Latency 14 cycles DDR LVDS MODE(4) tsu Data setup time(5) Data valid (6) to zero-cross of CLKOUTP 1.0 1.5 ns Zero-cross of CLKOUTP to data becoming th Data hold time(5) 0.35 0.8 ns invalid(6) (1) Timing parameters are specified by design and characterization and not tested in production. (2) CL is the effective external single-ended load capacitance between each output pin and ground. (3) IO refers to the LVDS buffer current setting; RL is the differential load resistance between the LVDS output pair. (4) Measurements are done with a transmission line of 100 Ω characteristic impedance between the device and the load. (5) Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume that the data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as reduced timing margin. (6) Data valid refers to logic high of +50 mV and logic low of –50 mV. Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): ADS5517 |
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