ADG824 datasheet(7/16 Pages) AD

No. de pieza	ADG824

Descripción Electrónicos	0.5 廓 CMOS 1.65 V to 3.6 V Dual SPDT/2:1 Mux in Mini LFCSP Package

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Fabricante Electrónico	AD [Analog Devices]

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7 / 16 page

ADG824

Rev. 0 | Page 7 of 16

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

S2B

D1

S1B

D2

ADG824

TOP VIEW

(Not to Scale)

2

3

8

7

PIN 1

INDICATOR

Figure 2. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

S1A

Source Terminal. This pin can be an input or an output.

2

D1

Drain Terminal. This pin can be an input or an output.

3

S1B

Source Terminal. This pin can be an input or an output.

4

IN1

Logic Control Input. This pin controls Switch S1A and Switch S1B to D1.

5

IN2

Logic Control Input. This pin controls Switch S2A and Switch S2B to D2.

6

VDD

Most Positive Power Supply Potential.

7

S2B

Source Terminal. This pin can be an input or an output.

8

D2

Drain Terminal. This pin can be an input or an output.

9

S2A

Source Terminal. This pin can be an input or an output.

10

GND

Ground (0 V) Reference.

Table 6. ADG824 Truth Table

Logic (IN1/IN2)

Switch A (S1A or S2A)

Switch B (S1B or S2B)

0

Off

On

1

On

Off

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