Motor de Búsqueda de Datasheet de Componentes Electrónicos
Selected language     Spanish  ▼

Delete All
ON OFF
ALLDATASHEET.ES

X  

Preview PDF Download HTML

CAT1021_0711 Datasheet(PDF) 5 Page - Catalyst Semiconductor

No. de Pieza. CAT1021_0711
Descripción  Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer
Descarga  21 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Fabricante  CATALYST [Catalyst Semiconductor]
Página de inicio  http://www.catalyst-semiconductor.com
Logo 

CAT1021_0711 Datasheet(HTML) 5 Page - Catalyst Semiconductor

 
Zoom Inzoom in Zoom Outzoom out
 5 / 21 page
background image
CAT1021, CAT1022, CAT1023
© Catalyst Semiconductor, Inc.
5
Doc. No. MD-3009 Rev. M
Characteristics subject to change without notice
CAPACITANCE
TA = 25ºC, f = 1.0MHz, VCC = 5V
Symbol
Test
Test Conditions
Max
Units
COUT
(1)
Output Capacitance
VOUT = 0V
8
pF
CIN
(1)
Input Capacitance
VIN = 0V
6
pF
AC CHARACTERISTICS
V
CC = 2.7V to 5.5V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle
(2)
Symbol
Parameter
Min
Max
Units
fSCL
Clock Frequency
400
kHz
tSP
Input Filter Spike Suppression (SDA, SCL)
100
ns
tLOW
Clock Low Period
1.3
µs
tHIGH
Clock High Period
0.6
µs
tR
(1)
SDA and SCL Rise Time
300
ns
tF
(1)
SDA and SCL Fall Time
300
ns
tHD; STA
Start Condition Hold Time
0.6
µs
tSU; STA
Start Condition Setup Time (for a Repeated Start)
0.6
µs
tHD; DAT
Data Input Hold Time
0
ns
tSU; DAT
Data Input Setup Time
100
ns
tSU; STO
Stop Condition Setup Time
0.6
µs
tAA
SCL Low to Data Out Valid
900
ns
tDH
Data Out Hold Time
50
ns
tBUF
(1)
Time the Bus must be Free Before a New Transmission Can Start
1.3
µs
tWC
(3)
Write Cycle Time (Byte or Page)
5
ms
Notes:
(1) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(2) Test Conditions according to “AC Test Conditions” table.
(3) The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21 


Datasheet Download




Enlace URL




Privacy Policy
ALLDATASHEET.ES
Does ALLDATASHEET help your business so far?  [ DONATE ]  

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Favorito   |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn