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STK22C48-NF45ITR Datasheet(PDF) 8 Page - Simtek Corporation

No. de pieza STK22C48-NF45ITR
Descripción Electrónicos  2Kx8 AutoStore nvSRAM
Download  16 Pages
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Fabricante Electrónico  SIMTEK [Simtek Corporation]
Página de inicio  http://www.simtek.com
Logo SIMTEK - Simtek Corporation

STK22C48-NF45ITR Datasheet(HTML) 8 Page - Simtek Corporation

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8
Feb, 2008
Document Control #ML0004 Rev 2.0
STK22C48
nvSRAM OPERATION
The STK22C48 has two separate modes of opera-
tion: SRAM mode and nonvolatile mode. In SRAM
mode, the memory operates as a standard fast static
RAM
. In nonvolatile mode, data is transferred from
SRAM
to Nonvolatile Elements (the STORE opera-
tion) or from Nonvolatile Elements to SRAM (the
RECALL
operation). In this mode SRAM functions are
disabled.
NOISE CONSIDERATIONS
The STK22C48 is a high-speed memory and so
must have a high-frequency bypass capacitor of
approximately 0.1
μF connected between V
CAP and
V
SS, using leads and traces that are as short as pos-
sible. As with all high-speed CMOS ICs, normal care-
ful routing of power, ground and signals will help
prevent noise problems.
SRAM READ
The STK22C48 performs a READ cycle whenever E
and G are low and W and HSB are high. The
address specified on pins A
0-10 determines which of
the 2,048 data bytes will be accessed. When the
READ
is initiated by an address transition, the out-
puts will be valid after a delay of t
AVQV (READ cycle
#1). If the READ is initiated by E or G, the outputs will
be valid at t
ELQV or at tGLQV, whichever is later (READ
cycle #2). The data outputs will repeatedly respond to
address changes within the t
AVQV access time without
the need for transitions on any control input pins, and
will remain valid until another address change or until
E or G is brought high, or W or HSB is brought low.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low and HSB is high. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on the common I/O pins
DQ
0-7 will be written into the memory if it is valid tDVWH
before the end of a W controlled WRITE or t
DVEH
before the end of an E controlled WRITE.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
common I/O lines. If G is left low, internal circuitry
will turn off the output buffers t
WLQZ after W goes low.
POWER-UP RECALL
During power up, or after any low-power condition
(V
CAP < VRESET), an internal RECALL request will be
latched. When V
CAP once again exceeds the sense
voltage of V
SWITCH, a RECALL cycle will automatically
be initiated and will take t
RESTORE to complete.
If the STK22C48 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
V
CC or between E and system VCC.
AutoStore MODE
The STK22C48 can be powered in one of three
modes.
During normal AutoStore operation, the STK22C48
will draw current from V
CC to charge a capacitor con-
nected to the V
CAP pin. This stored charge will be
used by the chip to perform a single STORE opera-
tion. After power up, when the voltage on the V
CAP
pin drops below V
SWITCH, the part will automatically
disconnect the V
CAP
pin from V
CC
and initiate a
STORE
operation.
Figure 2 shows the proper connection of capacitors
for automatic store operation. A charge storage
capacitor having a capacity of between 68
μF and
220
μF (± 20%) rated at 6V should be provided.
In system power mode, both V
CC and VCAP are con-
nected to the + 5V power supply without the 68
μF
capacitor. In this mode the AutoStore function of the
Figure 2: AutoStore Mode
*If HSB is not used, it should be left unconnected.
1
16
32
31
17
30
+
10k
Ω∗


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