Motor de Búsqueda de Datasheet de Componentes Electrónicos
  Spanish  ▼
ALLDATASHEET.ES

X  

ADSP-BF531SBBC400 Datasheet(PDF) 7 Page - Analog Devices

No. de pieza ADSP-BF531SBBC400
Descripción Electrónicos  Blackfin짰 Embedded Processor
Download  60 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

ADSP-BF531SBBC400 Datasheet(HTML) 7 Page - Analog Devices

Back Button ADSP-BF531SBBC400 Datasheet HTML 3Page - Analog Devices ADSP-BF531SBBC400 Datasheet HTML 4Page - Analog Devices ADSP-BF531SBBC400 Datasheet HTML 5Page - Analog Devices ADSP-BF531SBBC400 Datasheet HTML 6Page - Analog Devices ADSP-BF531SBBC400 Datasheet HTML 7Page - Analog Devices ADSP-BF531SBBC400 Datasheet HTML 8Page - Analog Devices ADSP-BF531SBBC400 Datasheet HTML 9Page - Analog Devices ADSP-BF531SBBC400 Datasheet HTML 10Page - Analog Devices ADSP-BF531SBBC400 Datasheet HTML 11Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 60 page
background image
ADSP-BF531/ADSP-BF532/ADSP-BF533
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processor is saved on the
supervisor stack.
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor event
controller consists of two stages, the core event controller (CEC)
and the system interrupt controller (SIC). The core event con­
troller works with the system interrupt controller to prioritize
and control all system events. Conceptually, interrupts from the
peripherals enter into the SIC, and are then routed directly into
the general-purpose interrupts of the CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority inter­
rupts (IVG15–14) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
support the peripherals of the processor. Table 2 describes the
inputs to the CEC, identifies their names in the event vector
table (EVT), and lists their priorities.
Table 2. Core Event Controller (CEC)
Priority
(0 is Highest)
Event Class
EVT Entry
0
Emulation/Test Control
EMU
1
Reset
RST
2
Nonmaskable Interrupt
NMI
3
Exception
EVX
4
Reserved
5
Hardware Error
IVHW
6
Core Timer
IVTMR
7
General Interrupt 7
IVG7
8
General Interrupt 8
IVG8
9
General Interrupt 9
IVG9
10
General Interrupt 10
IVG10
11
General Interrupt 11
IVG11
12
General Interrupt 12
IVG12
13
General Interrupt 13
IVG13
14
General Interrupt 14
IVG14
15
General Interrupt 15
IVG15
System Interrupt Controller (SIC)
The system interrupt controller provides the mapping and rout­
ing of events from the many peripheral interrupt sources to the
prioritized general-purpose interrupt inputs of the CEC.
Although the ADSP-BF531/ADSP-BF532/ADSP-BF533 proces­
sor provides a default mapping, the user can alter the mappings
and priorities of interrupt events by writing the appropriate val­
ues into the interrupt assignment registers (SIC_IARx). Table 3
describes the inputs into the SIC and the default mappings into
the CEC.
Table 3. System Interrupt Controller (SIC)
Peripheral Interrupt Event
Default Mapping
PLL Wakeup
IVG7
DMA Error
IVG7
PPI Error
IVG7
SPORT 0 Error
IVG7
SPORT 1 Error
IVG7
SPI Error
IVG7
UART Error
IVG7
Real-Time Clock
IVG8
DMA Channel 0 (PPI)
IVG8
DMA Channel 1 (SPORT 0 Receive)
IVG9
DMA Channel 2 (SPORT 0 Transmit)
IVG9
DMA Channel 3 (SPORT 1 Receive)
IVG9
DMA Channel 4 (SPORT 1 Transmit)
IVG9
DMA Channel 5 (SPI)
IVG10
DMA Channel 6 (UART Receive)
IVG10
DMA Channel 7 (UART Transmit)
IVG10
Timer 0
IVG11
Timer 1
IVG11
Timer 2
IVG11
Port F GPIO Interrupt A
IVG12
Port F GPIO Interrupt B
IVG12
Memory DMA Stream 0
IVG13
Memory DMA Stream 1
IVG13
Software Watchdog Timer
IVG13
Event Control
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor pro­
vides the user with a very flexible mechanism to control the
processing of events. In the CEC, three registers are used to
coordinate and control events. Each register is 32 bits wide:
• CEC interrupt latch register (ILAT) – The ILAT register
indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and
cleared when the event has been accepted into the system.
This register is updated automatically by the controller, but
it may also be written to clear (cancel) latched events. This
register may be read while in supervisor mode and may
only be written while in supervisor mode when the corre­
sponding IMASK bit is cleared.
• CEC interrupt mask register (IMASK) – The IMASK regis­
ter controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event is
unmasked and will be processed by the CEC when asserted.
A cleared bit in the IMASK register masks the event,
preventing the processor from servicing the event even
though the event may be latched in the ILAT register. This
register may be read or written while in supervisor mode.
Rev. E
|
Page 7 of 60
|
July 2007


Número de pieza similar - ADSP-BF531SBBC400

Fabricante ElectrónicoNo. de piezaDatasheetDescripción Electrónicos
logo
Analog Devices
ADSP-BF531SBBC400 AD-ADSP-BF531SBBC400 Datasheet
671Kb / 56P
   Blackfin Embedded Processor
REV. 0
ADSP-BF531SBBC400 AD-ADSP-BF531SBBC400 Datasheet
2Mb / 60P
   Blackfin Embedded Processor
REV. D
ADSP-BF531SBBC400 AD-ADSP-BF531SBBC400 Datasheet
2Mb / 64P
   Blackfin Embedded Processor
Rev. H
ADSP-BF531SBBC400 AD-ADSP-BF531SBBC400 Datasheet
2Mb / 64P
   Blackfin Embedded Processor
Rev. I
More results

Descripción similar - ADSP-BF531SBBC400

Fabricante ElectrónicoNo. de piezaDatasheetDescripción Electrónicos
logo
Analog Devices
ADSP-BF538 AD-ADSP-BF538_07 Datasheet
2Mb / 56P
   Blackfin짰 Embedded Processor
REV. 0
ADSP-BF561 AD-ADSP-BF561_07 Datasheet
3Mb / 64P
   Blackfin짰 Embedded Symmetric Multiprocessor
REV. B
ADSP-BF542 AD-ADSP-BF542 Datasheet
1Mb / 64P
   Embedded Processor
Rev. PrG
logo
Applied Micro Circuits ...
405EXR AMCC-405EXR Datasheet
176Kb / 2P
   Embedded Processor
logo
Analog Devices
ADSP-BF542 AD-ADSP-BF542_07 Datasheet
3Mb / 68P
   Embedded Processor
Rev. PrE
ADSP-BF542 AD-ADSP-BF542_1 Datasheet
3Mb / 100P
   Embedded Processor
Rev. C
ADSP-21266 AD-ADSP-21266_07 Datasheet
894Kb / 44P
   Embedded Processor
REV. C
ADSP-BF522C AD-ADSP-BF522C Datasheet
829Kb / 12P
   Embedded Processor
Rev. PrB
ADSP-TS101S AD-ADSP-TS101S Datasheet
827Kb / 44P
   Embedded Processor
REV. A
ADSP-21262 AD-ADSP-21262_05 Datasheet
1Mb / 48P
   Embedded Processor
REV. B
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Datasheet Descarga

Go To PDF Page


Enlace URL




Política de Privacidad
ALLDATASHEET.ES
¿ALLDATASHEET es útil para Ud.?  [ DONATE ] 

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com