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ADSP-BF531SBST400 Datasheet(PDF) 9 Page - Analog Devices |
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ADSP-BF531SBST400 Datasheet(HTML) 9 Page - Analog Devices |
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9 / 60 page  ADSP-BF531/ADSP-BF532/ADSP-BF533 The stopwatch function counts down from a programmed value, with one second resolution. When the stopwatch is enabled and the counter underflows, an interrupt is generated. Like other peripherals, the RTC can wake up the processor from sleep mode upon generation of any RTC wakeup event. Additionally, an RTC wakeup event can wake up the processor from deep sleep mode, and wake up the on-chip internal voltage regulator from a powered-down state. Connect RTC pins RTXI and RTXO with external components as shown in Figure 6. RTXI RTXO R1 X1 C1 C2 SUGGESTED COMPONENTS: X1 = ECL IPTEK E C38J (THROUGH-HOLE PACKAGE) OR EPSO N MC405 12 pF LOAD (S URFACE-MO UNT PACKAGE) C1 = 22pF C2 = 22pF R1 = 10M Ω NOTE : C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECI FIED FOR X1. CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2 SPECI FI CATIO NS ASSUME BOARD TRACE CAPACITANCE OF 3pF. Figure 6. External Components for RTC WATCHDOG TIMER The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor includes a 32-bit timer that can be used to implement a software watchdog function. A software watchdog can improve system availability by forcing the processor to a known state through generation of a hardware reset, nonmaskable interrupt (NMI), or general-purpose interrupt, if the timer expires before being reset by software. The programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts to zero from the programmed value. This protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error. If configured to generate a hardware reset, the watchdog timer resets both the core and the processor peripherals. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register. The timer is clocked by the system clock (SCLK), at a maximum frequency of f SCLK. TIMERS There are four general-purpose programmable timer units in the ADSP-BF531/ADSP-BF532/ADSP-BF533 processor. Three timers have an external pin that can be configured either as a pulse-width modulator (PWM) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. These timers can be synchro nized to an external clock input to the PF1 pin (TACLK), an external clock input to the PPI_CLK pin (TMRCLK), or to the internal SCLK. The timer units can be used in conjunction with the UART to measure the width of the pulses in the data stream to provide an autobaud detect function for a serial channel. The timers can generate interrupts to the processor core provid ing periodic events for synchronization, either to the system clock or to a count of external signals. In addition to the three general-purpose programmable timers, a fourth timer is also provided. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts. SERIAL PORTS (SPORTs) The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor incor porates two dual-channel synchronous serial ports (SPORT0 and SPORT1) for serial and multiprocessor communications. The SPORTs support the following features: • I2S capable operation. • Bidirectional operation – Each SPORT has two sets of inde pendent transmit and receive pins, enabling eight channels of I2S stereo audio. • Buffered (8-deep) transmit and receive ports – Each port has a data register for transferring data words to and from other processor components and shift registers for shifting data in and out of the data registers. • Clocking – Each transmit and receive port can either use an external serial clock or generate its own, in frequencies ranging from (f SCLK/131,070) Hz to (fSCLK/2) Hz. • Word length – Each SPORT supports serial data words from 3 bits to 32 bits in length, transferred most-signifi cant-bit first or least-significant-bit first. • Framing – Each transmit and receive port can run with or without frame sync signals for each data word. Frame sync signals can be generated internally or externally, active high or low, and with either of two pulse widths and early or late frame sync. • Companding in hardware – Each SPORT can perform A-law or μ-law companding according to ITU recommen dation G.711. Companding can be selected on the transmit and/or receive channel of the SPORT without additional latencies. • DMA operations with single-cycle overhead – Each SPORT can automatically receive and transmit multiple buffers of memory data. The processor can link or chain sequences of DMA transfers between a SPORT and memory. Rev. E | Page 9 of 60 | July 2007 |
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