Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 369
Figure 15-13. Slave Command Sequence ............................................................................................ 370
Figure 16-1.
CAN Module Block Diagram ........................................................................................... 395
Figure 16-2.
CAN Bit Time ................................................................................................................ 402
Figure 17-1.
Ethernet Controller Block Diagram .................................................................................. 439
Figure 17-2.
Ethernet Controller ......................................................................................................... 439
Figure 17-3.
Ethernet Frame ............................................................................................................. 441
Figure 18-1.
Analog Comparator Module Block Diagram ..................................................................... 483
Figure 18-2.
Structure of Comparator Unit .......................................................................................... 484
Figure 18-3.
Comparator Internal Reference Structure ........................................................................ 485
Figure 19-1.
Pin Connection Diagram ................................................................................................ 495
Figure 22-1.
Load Conditions ............................................................................................................ 513
Figure 22-2.
I
2C Timing ..................................................................................................................... 516
Figure 22-3.
External XTLP Oscillator Characteristics ......................................................................... 518
Figure 22-4.
Hibernation Module Timing ............................................................................................. 519
Figure 22-5.
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 520
Figure 22-6.
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 520
Figure 22-7.
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 521
Figure 22-8.
JTAG Test Clock Input Timing ......................................................................................... 522
Figure 22-9.
JTAG Test Access Port (TAP) Timing .............................................................................. 522
Figure 22-10. JTAG TRST Timing ........................................................................................................ 522
Figure 22-11. External Reset Timing (RST) ........................................................................................... 523
Figure 22-12. Power-On Reset Timing ................................................................................................. 524
Figure 22-13. Brown-Out Reset Timing ................................................................................................ 524
Figure 22-14. Software Reset Timing ................................................................................................... 524
Figure 22-15. Watchdog Reset Timing ................................................................................................. 524
Figure 23-1.
100-Pin LQFP Package .................................................................................................. 525
June 14, 2007
10
Luminary Micro Confidential-Advance Product Information
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