List of Figures
Figure 1-1.
Stellaris
® 6000 Series High-Level Block Diagram ............................................................... 27
Figure 2-1.
CPU Block Diagram ......................................................................................................... 35
Figure 2-2.
TPIU Block Diagram ........................................................................................................ 36
Figure 5-1.
JTAG Module Block Diagram ............................................................................................ 45
Figure 5-2.
Test Access Port State Machine ....................................................................................... 48
Figure 5-3.
IDCODE Register Format ................................................................................................. 53
Figure 5-4.
BYPASS Register Format ................................................................................................ 54
Figure 5-5.
Boundary Scan Register Format ....................................................................................... 54
Figure 6-1.
External Circuitry to Extend Reset .................................................................................... 56
Figure 7-1.
Hibernation Module Block Diagram ................................................................................. 114
Figure 8-1.
Flash Block Diagram ...................................................................................................... 132
Figure 9-1.
GPIO Port Block Diagram ............................................................................................... 157
Figure 9-2.
GPIODATA Write Example ............................................................................................. 158
Figure 9-3.
GPIODATA Read Example ............................................................................................. 158
Figure 10-1.
GPTM Module Block Diagram ........................................................................................ 198
Figure 10-2.
16-Bit Input Edge Count Mode Example .......................................................................... 202
Figure 10-3.
16-Bit Input Edge Time Mode Example ........................................................................... 203
Figure 10-4.
16-Bit PWM Mode Example ............................................................................................ 204
Figure 11-1.
WDT Module Block Diagram .......................................................................................... 233
Figure 12-1.
ADC Module Block Diagram ........................................................................................... 257
Figure 13-1.
UART Module Block Diagram ......................................................................................... 289
Figure 13-2.
UART Character Frame ................................................................................................. 290
Figure 13-3.
IrDA Data Modulation ..................................................................................................... 292
Figure 14-1.
SSI Module Block Diagram ............................................................................................. 329
Figure 14-2.
TI Synchronous Serial Frame Format (Single Transfer) .................................................... 331
Figure 14-3.
TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 332
Figure 14-4.
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 333
Figure 14-5.
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 333
Figure 14-6.
Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 334
Figure 14-7.
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 335
Figure 14-8.
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 335
Figure 14-9.
Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 336
Figure 14-10. MICROWIRE Frame Format (Single Frame) .................................................................... 337
Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 338
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 338
Figure 15-1.
I2C Block Diagram ......................................................................................................... 366
Figure 15-2.
I2C Bus Configuration .................................................................................................... 367
Figure 15-3.
START and STOP Conditions ......................................................................................... 367
Figure 15-4.
Complete Data Transfer with a 7-Bit Address ................................................................... 368
Figure 15-5.
R/S Bit in First Byte ........................................................................................................ 368
Figure 15-6.
Data Validity During Bit Transfer on the I2C Bus ............................................................... 368
Figure 15-7.
Master Single SEND ...................................................................................................... 371
Figure 15-8.
Master Single RECEIVE ................................................................................................. 372
Figure 15-9.
Master Burst SEND ....................................................................................................... 373
Figure 15-10. Master Burst RECEIVE .................................................................................................. 374
November 30, 2007
8
Preliminary
Table of Contents