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ST6215CM6 Datasheet(PDF) 34 Page - STMicroelectronics |
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ST6215CM6 Datasheet(HTML) 34 Page - STMicroelectronics |
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34 / 70 page  34/70 ST62T15C/T25C/E25C I/O PORTS (Cont’d) 4.1.2 Safe I/O State Switching Sequence Switching the I/O ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur. The recom- mended safe transitions are illustrated in Figure 23. All other transitions are potentially risky and should be avoided when changing the I/O operat- ing mode, as it is most likely that undesirable side- effects will be experienced, such as spurious inter- rupt generation or two pins shorted together by the analog multiplexer. Single bit instructions (SET, RES, INC and DEC) should be used with great caution on Ports Data registers, since these instructions make an implicit read and write back of the entire register. In port input mode, however, the data register reads from the input pins directly, and not from the data regis- ter latches. Since data register information in input mode is used to set the characteristics of the input pin (interrupt, pull-up, analog input), these may be unintentionally reprogrammed depending on the state of the input pins. As a general rule, it is better to limit the use of single bit instructions on data registers to when the whole (8-bit) port is in output mode. In the case of inputs or of mixed inputs and outputs, it is advisable to keep a copy of the data register in RAM. Single bit instructions may then be used on the RAM copy, after which the whole copy register can be written to the port data regis- ter: SET bit, datacopy LD a, datacopy LD DRA, a Warning: Care must also be taken to not use in- structions that act on a whole port register (INC, DEC, or read operations) when all 8 bits are not available on the device. Unavailable bits must be masked by software (AND instruction). The WAIT and STOP instructions allow the ST62xx to be used in situations where low power consumption is needed. The lowest power con- sumption is achieved by configuring I/Os in input mode with well-defined logic levels. The user must take care not to switch outputs with heavy loads during the conversion of one of the analog inputs in order to avoid any disturbance to the conversion. Figure 23. Diagram showing Safe I/O State Transitions Note *. xxx = DDR, OR, DR Bits respectively Interrupt pull-up Output Open Drain Output Push-pull Input pull-up (Reset state) Input Analog Output Open Drain Output Push-pull Input 010* 000 100 110 011 001 101 111 34 |
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