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ST6232BB3 Datasheet(PDF) 5 Page - STMicroelectronics |
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ST6232BB3 Datasheet(HTML) 5 Page - STMicroelectronics |
5 / 86 page 5/86 ST62T32B ST62E32B 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST62T32B and ST62E32B devices are low cost members of the ST62xx 8-bit HCMOS family of microcontrollers, which is targeted at low to me- dium complexity applications. All ST62xx devices are based on a building block approach: a com- mon core is surrounded by a number of on-chip peripherals. The ST62E32B is the erasable EPROM version of the ST62T32B device, which may be used to em- ulate the ST62T32B device, as well as the respec- tive ST6232B ROM devices. Figure 1. Block Diagram TEST NMI INTERRUP T PROGRAM PC STACK LEVEL 1 STACK LEVEL 2 STACK LEVEL 3 STACK LEVEL 4 STACK LEVEL 5 STACK LEVEL 6 POWER SUPP LY OSCILLATOR RESET DATA ROM USER SELECTA BLE DATA RAM PORT A PORT B TIMER DIGITAL 8 BIT CORE TEST/VPP 8-BIT A/D CONVERTE R PA0..PA1 / 20 mA Sink VDD VSS OSCin OSCout RESET WATCHDOG Memory PORT C SPI (SERIAL PERIPHERAL INTERFAC E) AUTORELOA D TIMER 192 Bytes 7948 bytes DATA EEPR OM 128 Bytes PA2/OVF / 20 mA Sink PA3/PWM/20 mA Sink PA4/Ain/CP1 PA5/Ain/CP2 PB0/Ain PB3..PB7/Ain PC5..PC7/Ain PORT D PORT E PD0,PD6,PD7/Ain PD1/Ain/Scl PD2/Ain/Sin PD3/Ain/Sout PD4/Ain/RX D1 PD5/Ain/T XD1 PE0...PE4 PA6...PA7/Ain (VPP on EPROM/OT P versions only) TIMER VR01823E UART 109 |
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