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ST62T53B Datasheet(PDF) 27 Page - STMicroelectronics |
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ST62T53B Datasheet(HTML) 27 Page - STMicroelectronics |
27 / 75 page 27/75 ST62T53B/T60B/T63B ST62E60B 3.4 INTERRUPTS The CPU can manage four Maskable Interrupt sources, in addition to a Non Maskable Interrupt source (top priority interrupt). Each source is asso- ciated with a specific Interrupt Vector which con- tains a Jump instruction to the associated interrupt service routine. These vectors are located in Pro- gram space (see Table 9). When an interrupt source generates an interrupt request, and interrupt processing is enabled, the PC register is loaded with the address of the inter- rupt vector (i.e. of the Jump instruction), which then causes a Jump to the relevant interrupt serv- ice routine, thus servicing the interrupt. Interrupt sources are linked to events either on ex- ternal pins, or on chip peripherals. Several events can be ORed on the same interrupt source, and relevant flags are available to determine which event triggered the interrupt. The Non Maskable Interrupt request has the high- est priority and can interrupt any interrupt routine at any time; the other four interrupts cannot inter- rupt each other. If more than one interrupt request is pending, these are processed by the processor core according to their priority level: source #1 has the higher priority while source #4 the lower. The priority of each interrupt source is fixed. Table 9. Interrupt Vector Map 3.4.1 Interrupt request All interrupt sources but the Non Maskable Inter- rupt source can be disabled by setting accordingly the GEN bit of the Interrupt Option Register (IOR). This GEN bit also defines if an interrupt source, in- cluding the Non Maskable Interrupt source, can re- start the MCU from STOP/WAIT modes. Interrupt request from the Non Maskable Interrupt source #0 is latched by a flip flop which is automat- ically reset by the core at the beginning of the non- maskable interrupt service routine. Interrupt request from source #1 can be config- ured either as edge or level sensitive by setting ac- cordingly the LES bit of the Interrupt Option Regis- ter (IOR). Interrupt request from source #2 are always edge sensitive. The edge polarity can be configured by setting accordingly the ESB bit of the Interrupt Op- tion Register (IOR). Interrupt request from sources #3 & #4 are level sensitive. In edge sensitive mode, a latch is set when a edge occurs on the interrupt source line and is cleared when the associated interrupt routine is started. So, the occurrence of an interrupt can be stored, until completion of the running interrupt routine be- fore being processed. If several interrupt requests occurs before completion of the running interrupt routine, only the first request is stored. Storage of interrupt requests is not available in lev- el sensitive mode. To be taken into account, the low level must be present on the interrupt pin when the MCU samples the line after instruction execu- tion. At the end of every instruction, the MCU tests the interrupt lines: if there is an interrupt request the next instruction is not executed and the appropri- ate interrupt service routine is executed instead. Table 10. Interrupt Option Register Description Interrupt Source Priority Vector Address Interrupt source #0 1 (FFCh-FFDh) Interrupt source #1 2 (FF6h-FF7h) Interrupt source #2 3 (FF4h-FF5h) Interrupt source #3 4 (FF2h-FF3h) Interrupt source #4 5 (FF0h-FF1h) GEN SET Enable all interrupts CLEARED Disable all interrupts ESB SET Rising edge mode on inter- rupt source #2 CLEARED Falling edge mode on inter- rupt source #2 LES SET Level-sensitive mode on in- terrupt source #1 CLEARED Falling edge mode on inter- rupt source #1 OTHERS NOT USED 27 |
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