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ST62T63B Datasheet(PDF) 50 Page - STMicroelectronics |
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ST62T63B Datasheet(HTML) 50 Page - STMicroelectronics |
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50 / 75 page  50/75 ST62T53B/T60B/T63B ST62E60B SERIAL PERIPHERAL INTERFACE SPI(Cont’d) 4.5.1 SPI Registers SPI Mode Control Register (MOD) Address: E2h — Read/Write Reset status: 00h The MOD register defines and controls the trans- mission modes and characteristics. This register is read/write and all bits are cleared at reset. Setting SPSTRT = 1 and SPIN = 1 is not allowed and must be avoided. Bit 7 = SPRUN: SPI Run. This bit is the SPI activity flag. This can be used in either transmit or receive modes; it is automatically cleared by the SPI at the end of a transmission or reception and generates an interrupt request (providing that the SPIE Inter- rupt Enable bit is set). The Core can stop transmis- sion or reception at any time by resetting the SPRUN bit; this will also generate an interrupt re- quest (providing that the SPIE Interrupt enable bit is set). The SPRUN bit can be used as a start con- dition parameter, in conjunction with the SPSTRT bit, when an external signal is present on the Sin pin. Note that a rising edge is then necessary to in- itiate reception; this may require external data in- version. Bit 6 = SPIE: SPI Interrupt Enable. This bit is the SPI Interrupt Enable bit. If this bit is set the SPI in- terrupt (vector #2) is enabled, when SPIE is reset, the interrupt is disabled. Bit 5 = CPHA: Clock Phase Selection. This bit se- lects the clock phase of the clock signal. If this bit is cleared to zero the normal state is selected; in this case Bit 7 of the data frame is present on Sout pin as soon as the SPI Shift Register is loaded. If this bit is set to one the shifted state’ is selected; in this case Bit 7 of data frame is present on Sout pin on the first falling edge of Shift Register clock. The polarity relation and the division ratio between Shift Register and SPI base clock are also pro- grammable; refer to DIV register and Timing Dia- grams for more information. Bit 4= SPCLK: Base Clock Selection This bit selects the SPI base clock source. It is ei- ther the core cycle clock (fINT/13) (Master mode) or the signal provided at SCK pin by an external device (slave mode). If SPCLK is low and the SCK pin is configured as input, the slave mode is se- lected. If SPCLK is high and the SCK pin is config- ured as output, the master mode is selected. In this case, the phase and polarity of the clock are controlled by CPOL and CPHA. Bit 3 = SPIN: Input Selection This bit enables the transfer of the data input to the Shift Register in receive mode. If this bit is cleared the Shift Register input is 0. If this bit is set, the Shift Register input corresponds to the input signal present on the Sin pin. Bit 2 = SPSTRT: Start Selection This bit selects the transmission or reception start mode. If SPSTRT is cleared, the internal start con- dition occurs as soon as the SPRUN bit is set. If SPSTRT is set, the internal start signal is the logic “AND” between the SPRUN bit and the external signal present on the Sin pin; in this case transmis- sion will start after the latest of both signals provid- ing that the first signal is still present (note that this implies a rising edge). After the transmission or re- cetion has been started, it will continue even if the Sin signal is reset. Bit 1 = EFILT: Enable Filters This bit enables/disables the input noise filters on the Sin and SCK inputs. If it is cleared to zero the filters are enabled, if set to one the filters are disa- bled. These noise filters will eliminate any pulse on Sin and SCK with a pulse width smaller than one to two Core clock periods (depending on the oc- currence of the signal edge with respect to the Core clock edge). For example, if the ST6260B/ 65B runs with an 8MHz crystal, Sin and SCK will be delayed by 125 to 250ns. Bit 0 = CPOL: Clock Polarity This bit controls the relationship between the data on the Sin and Sout pins and SCK. The CPOL bit selects the clock edge which captures data and al- lows it to change state. It has the greatest impact on the first bit transmitted (the MSB) as it does (or does not) allow a clock transition before the first data capture edge. Refer to the timing diagrams at the end of this sec- tion for additional details. These show the relation- ship between CPOL, CPHA and SCK, and indicate the active clock edges and strobe times. 70 SPRUN SPIE CPHA SPCLK SPIN SPSTRT EFILT CPOL 50 |
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