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ST6393 Datasheet(PDF) 11 Page - STMicroelectronics |
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ST6393 Datasheet(HTML) 11 Page - STMicroelectronics |
11 / 68 page ST639x CORE The Core of the ST639x Family is implemented inde- pendently from the I/O or memory configuration. Consequently, it can be treated as an independent central processor communicating with I/O and mem- ory via internal addresses, data, and control busses. The in-core communication is arranged as shown in the following block diagram figure; the controller being externally linked to both the reset and the os- cillator, while the core is linked to the dedicated on- chip macrocells peripherals via the serial data bus and indirectly for interrupt purposes through the control registers. Registers The ST639x Family Core has five registers and three pairs of flags available to the programmer. They are shown in Figure 5 and are explained in the following paragraphs together with the pro- gram and data memory page registers. Accumulator (A). The accumulator is an 8-bit gen- eral purpose register used in all arithmetic calcula- tions, logical operations, and data manipulations. The accumulator is addressed in the data space as RAM location at the FFh address. Accordingly, the ST639x instruction set can use the accumulator as any other register of the data space. Figure 5. ST639x Core Block Diagram SHORT DIRECT ADDRESSING MODE V REGISTER W REGISTER PROGRAM COUNTER SIX LEVELS STACK REGISTER C C C Z Z Z NORMAL FLAGS INTERRUPT FLAGS NMI FLAGS INDEX REGISTER VA000423 b7 b7 b7 b7 b7 b0 b0 b0 b0 b0 b0 b11 ACCUMULATOR Y REG. POINTER X REG. POINTER Figure 6. ST639x Core Programming Model ® ST6391,92,93,95,97,99 7/64 |
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