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ST70235A Datasheet(PDF) 8 Page - STMicroelectronics |
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ST70235A Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 28 page ST70235A 8/28 PIN SUMMARY Mnemonic Type BS Type Number of Signals Function Power Supply VDD 3.3 VDD 1.8 (VSS + 3.3V) Power supply (VSS + 1.8V) Power supply VSS 0V Ground ATC INTERFACE ALE I C 1 Used to latch the address of the internal register to be accessed PCLK I I 1 Processor clock CSB I I 1 Chip selected to respond to bus cycle BE1 I I 1 Address 1 (not multiplexed) WR_RDB I I 1 Specifies the direction of the access cycle RDYB OZ O 1 Controls the ATC bus cycle termination INTB O O 1 Requests ATC interrupt service AD IO B 16 Multiplexed Address/Data bus OBC_TYPE I-PD I 1 Select between i960 (0) or generic (1) controller interface TEST ACCESS PART INTERFACE TDI I-PU 1 Refer to section TDO OZ 1 TCK I-PD 1 TMS I-PU 1 TRSTB I-PD 1 ANALOG FRONT END INTERFACE AFRXD I I 4 Receive data nibble AFTXD O O 4 Transmit data nibble CLWD I I 1 Start of word indication PDOWN O O 1 Power down analog front end CTRLDATA O O 1 Serial data transmit channel MCLK I C 1 Master cloc ATM UTOPIA INTERFACE U_RxData OZ B 8 Receive interface Data U_TxData I I 8 Transmit interface Data U_RxADDR I I 5 Receive interface Address U_TxADDR I I 5 Transmit interface Address U_RxCLAV OZ O 1 Receive interface Cell Available U_TxCLAV OZ O 1 Transmit interface Cell Available U_RxENBB I-TTL I 1 Receive interface Enable U_TxENBB I-TTL I 1 Transmit interface Enable U_RxSOC OZ O 1 Receive interface Start of Cell U_TxSOC I-TTL I 1 Transmit interface Start of Cell U_RxCLK I-TTL C 1 Receive interface Utopia Clock U_TxCLK I-TTL C 1 Transmit interface Utopia Clock U_RxRefB O O 1 8kHz reference clock to ATM device U_TxRefB I-TTL I 1 8kHz reference clock from ATM device |
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Descripción similar - ST70235A |
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