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ST95010M3TR Datasheet(PDF) 10 Page - STMicroelectronics

No. de pieza ST95010M3TR
Descripción Electrónicos  4K/2K/1K Serial SPI EEPROM with Positive Clock Strobe
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST95010M3TR Datasheet(HTML) 10 Page - STMicroelectronics

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DATA PROTECTION AND PROTOCOL SAFETY
– All inputs are protected against noise, see Table
6.
– Non valid S and HOLD transitions are not taken
into account.
– S must come high at the proper clock count in
order to start a non-volatile write cycle (in the
memory array or in the status register), that is
the Chip Select S mustrise during the clock pulse
following the introduction of a multiple of 8 bits.
– Access to the memory array during non-volatile
programming cycle is ignored; however, the pro-
gramming cycle continues.
– After any of the operations WREN, WRDI, RDSR
is completed, the chip enters a wait state and
waits for a deselect.
– The write enable latch is reset upon power-up.
– The write enable latch is reset when W is brought
low.
INITIAL DELIVERY STATE
The device is delivered with the memory array in a
fully erased state (all data set at all ”1’s” or FFh).
The block protect bits are initialized to 00.
AI01446
MASTER
ST95xxx
D
Q
C
CQ
D
S
ST95xxx
CQ
D
S
ST95xxx
CQ
D
S
CS3
CS2
CS1
Figure 12. EEPROM and SPI Bus
10/18
ST95040, ST95020, ST95010


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