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ADS8519IDBRG4 Datasheet(PDF) 8 Page - Texas Instruments |
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ADS8519IDBRG4 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 27 page www.ti.com R/C BUSY STATUS (N+1)th Accquisition (N+1)th Conversion Error Correction Nth Conversion Error Correction Internal DATACLK (N−1)th Conversion Data DATA Nth Conversion Data (N+2)th Accquisition 1 2 16 2 16 D15 D0 D15 D0 TAG = 0 TAG = 0 TAG = 0 8 starts READ CS, EXT/INT, and TAG are tied low tw1 td1 tw2 td3 td11 td2 td3 tw1 td1 tw2 td11 td2 tconv tacq tconv tacq td4 td4 tc1 td5 td6 1 BUSY STATUS (N+1)th Accquisition (N+1)th Conversion Error Correction Nth Conversion Error Correction External DATACLK DATA Nth Data (N+1)th Data (N+2)th Accquisition TAG = 0 No more data to shift out No more data to shift out TAG = 0 TAG = 0 TAG = 0 TAG = 0 R/C EXT/INT tied high, CS and TAG are tied low tw1 + tsu1 starts READ tw1 tw1 td1 tw2 td1 tw2 td3 td11 td2 td3 td11 td2 tsu1 tconv tacq tconv tacq tsu3 tsu1 tsu3 1 16 1 2 16 1 16 1 2 16 ADS8519 SLAS462A – JUNE 2007 – REVISED MARCH 2008 TIMING DIAGRAMS (continued) Figure 2. Basic Conversion Timing: Internal DATACLK (Read Previous Data During Conversion) Figure 3. Basic Conversion Timing: External DATACLK 8 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8519 |
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