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AD7262BSTZ-RL7 Datasheet(PDF) 8 Page - Analog Devices

No. de pieza AD7262BSTZ-RL7
Descripción Electrónicos  1 MSPS, 12-Bit, Simultaneous Sampling SAR ADC with PGA and Four Comparators
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

AD7262BSTZ-RL7 Datasheet(HTML) 8 Page - Analog Devices

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AD7262
Rev. 0 | Page 8 of 32
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
AD7262
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
11
12
13
15 16 17 18 19 20 21 22 23 24
25
COUTD
26
COUTC
27
VDRIVE
28
DGND
29
COUTB
30
COUTA
31
DOUTB
32
DOUTA
33
AVCC
34
SCLK
35
CS
36
CAL
37
38
39
40
41
42
43
44
45
46
47
48
14
CA_CBVCC
AVCC
VA
VA+
AGND
AVCC
AGND
VB+
VB
AVCC
CC_CDVCC
AGND
AD7262
TOP VIEW
(Not to Scale)
COUTD
COUTC
VDRIVE
DGND
COUTB
COUTA
DOUTB
DOUTA
AVCC
SCLK
CAL
CS
1
2
3
4
5
6
7
8
9
10
11
12
35
36
34
33
32
31
30
29
28
27
26
25
PIN 1
INDICATOR
CA_CBVCC
AVCC
VA
VA+
AGND
AVCC
AGND
VB+
VB
AVCC
CC_CDVCC
AGND
NOTES
1. THE EXPOSED METAL PADDLE ON THE BOTTOM OF THE LFCSP PACKAGE MUST
BE SOLDERED TO PCB GROUND FOR PROPER HEAT DISSIPATION AND ALSO FOR
NOISE AND MECHANICAL STRENGTH BENEFITS.
Figure 3. 48-Lead LQFP Pin Configuration
Figure 4. 48-Lead LFCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
2, 7, 11, 20, 33, 41
AVCC
Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the analog circuitry on the
AD7262/AD7262-5. All AVCC pins can be tied together. This supply should be decoupled to AGND
with a 100 nF ceramic capacitor per supply and a 10 μF tantalum capacitor.
1
CA_CBVCC
Comparator Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for Comparator A and
Comparator B. This supply should be decoupled to CA_CB_GND. AVCC, CC_CDVCC, and CA_CBVCC can be
tied together.
12
CC_CDVCC
Comparator Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for Comparator C and
Comparator D. This supply should be decoupled to CC_CD_GND. AVCC, CC_CDVCC, and CA_CBVCC can be
tied together.
4, 3
VA+, VA
Analog Inputs of ADC A. True differential input pair.
9, 10
VB+, VB
Analog Inputs of ADC B. True differential input pair.
43, 18
VREFA, VREFB
Reference Input/Output. Decoupling capacitors are connected to these pins to decouple the
internal reference buffer for each respective ADC. Typically, 1 μF capacitors are required to decouple
the reference. Provided the output is buffered, the on-chip reference can be taken from these pins
and applied externally to the rest of a system.
34
SCLK
Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the
AD7262/AD7262-5. This clock is also used as the clock source for the conversion process. A
minimum of 31 clocks is required to perform the conversion and access the 12-bit result.
36
CAL
Logic Input. Initiates an internal offset calibration.
21
PD2
Logic Input. Places the AD7262/AD7262-5 in selected shutdown mode in conjunction with the PD1
and PD0 pins (see Table 7).
22
PD1
Logic Input. Places the AD7262/AD7262-5 in selected shutdown mode in conjunction with the PD2
and PD0 pins (see Table 7).


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