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ADUM1311 Datasheet(PDF) 3 Page - Analog Devices |
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ADUM1311 Datasheet(HTML) 3 Page - Analog Devices |
3 / 24 page ADuM1310/ADuM1311 Rev. G | Page 3 of 24 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V OPERATION 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. All voltages are relative to their respective grounds. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS ADuM1310, Total Supply Current, Three Channels1 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 2.4 3.2 mA DC to 1 MHz logic signal frequency VDD2 Supply Current IDD2 (Q) 1.2 1.6 mA DC to 1 MHz logic signal frequency 10 Mbps (BRWZ Grade Only) VDD1 Supply Current IDD1 (10) 6.6 9.0 mA 5 MHz logic signal frequency VDD2 Supply Current IDD2 (10) 2.1 3.0 mA 5 MHz logic signal frequency ADuM1311, Total Supply Current, Three Channels1 DC to 2 Mbps VDD1 Supply Current IDD1 (Q) 2.2 2.8 mA DC to 1 MHz logic signal frequency VDD2 Supply Current IDD2 (Q) 1.8 2.4 mA DC to 1 MHz logic signal frequency 10 Mbps (BRWZ Grade Only) VDD1 Supply Current IDD1 (10) 4.5 5.7 mA 5 MHz logic signal frequency VDD2 Supply Current IDD2 (10) 3.5 4.3 mA 5 MHz logic signal frequency For All Models Input Currents IIA, IIB, IIC, ICTRL1, ICTRL2, IDISABLE −10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2, 0 V ≤ VCTRL1, VCTRL2 ≤ VDD1 or VDD2, 0 V ≤ VDISABLE ≤ VDD1 Logic High Input Threshold VIH 2.0 V Logic Low Input Threshold VIL 0.8 V (VDD1 or VDD2) − 0.1 5.0 V IOx = −20 μA, VIx = VIxH Logic High Output Voltages VOAH, VOBH, VOCH (VDD1 or VDD2) − 0.4 4.8 V IOx = −4 mA, VIx = VIxH 0.0 0.1 V IOx = 20 μA, VIx = VIxL Logic Low Output Voltages VOAL, VOBL, VOCL 0.2 0.4 V IOx = 4 mA, VIx = VIxL SWITCHING SPECIFICATIONS ADuM131xARWZ Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 tPHL, tPLH 20 100 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns CL = 15 pF, CMOS signal levels Propagation Delay Skew5 tPSK 50 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching6 tPSKCD/OD 50 ns CL = 15 pF, CMOS signal levels ADuM131xBRWZ Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay4 tPHL, tPLH 20 30 50 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH − tPHL|4 PWD 5 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew5 tPSK 30 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, tPSKCD 5 ns CL = 15 pF, CMOS signal levels |
Número de pieza similar - ADUM1311 |
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Descripción similar - ADUM1311 |
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