REV. 0

–10–

ADuC814

Parameter

Min

Typ

Max

Unit

Figure

SPI MASTER MODE TIMING (CPHA = 0)

630

ns

5

630

ns

5

Data Output Valid after SCLOCK Edge

50

ns

5

Data Output Setup before SCLOCK Edge

150

ns

5

Data Input Setup Time before SCLOCK Edge

100

ns

5

Data Input Hold Time after SCLOCK Edge

100

ns

5

Data Output Fall Time

10

25

ns

5

Data Output Rise Time

10

25

ns

5

SCLOCK Rise Time

10

25

ns

5

SCLOCK Fall Time

10

25

ns

5

*

Characterized under the following conditions:

a. Core clock divider Bits CD2, CD1, and CD0 in PLLCON SFR set to 0, 1, and 1, respectively, i.e., core clock frequency = 2.09 MHz.

b. SPI bit rate selection Bits SPR1 and SPR0 in SPICON SFR set to 0 and 0, respectively.

SCLOCK

(CPOL = 0)

t

DSU

SCLOCK

(CPOL = 1)

MOSI

MISO

MSB

LSB

LSB IN

BITS 6–1

BITS 6–1

MSB IN

t

DHD

t

DR

t

DAV

t

DF

t

DOSU

t

SH

t

SL

t

SR

t

SF

Figure 5. SPI Master Mode Timing (CPHA = 0)