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STE100 Datasheet(Hoja de datos) 10 Page - STMicroelectronics

No. de Pieza. STE100
Descripción  PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V
Descarga  66 Pages
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Fabricante  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
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 10 page
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STE10/100
10/66
29
SMA
Status Master Abort.
1: means that STE10/100 received a master abort and has
terminated a master transaction.
0
R/W
28
STA
Status Target Abort.
1: means that STE10/100 received a target abort and has
terminated a master transaction.
0
R/W
27
---
Reserved.
26, 25
SDST
Status Device Select Timing. Indicates the timing of the chip’s
assertion of device select.
01: indicates a medium assertion of DEVSEL#
01
R/O
24
SDPR
Status Data Parity Report.
1: when three conditions are met:
a. STE10/100 asserted parity error (PERR#) or it detected
parity error asserted by another device.
b. STE10/100 is operating as a bus master.
c. STE10/100’s parity error response bit (bit 6 of CR1) is
enabled.
0
R/W
23
SFBB
Status Fast Back-to-Back
Always 1, since STE10/100 has the ability to accept fast back
to back transactions.
1
R/O
22~21
---
Reserved.
20
NC
New Capabilities. Indicates whether the STE10/100 provides a
list of extended capabilities, such as PCI power management.
1: the STE10/100 provides the PCI management function
0: the STE10/100 doesn’t provide New Capabilities.
Same as
bit 19 of
CSR18
RO
19~ 9
---
Reserved.
8
CSE
Command System Error Response
1: enable system error response. The STE10/100 will assert
SERR# when it finds a parity error during the address phase.
0
R/W
7
---
Reserved.
6
CPE
Command Parity Error Response
0: disable parity error response. STE10/100 will ignore any
detected parity error and keep on operating. Default value is
0.
1: enable parity error response. STE10/100 will assert system
error (bit 13 of CSR5) when a parity error is detected.
0
R/W
5~ 3
---
Reserved.
2
CMO
Command Master Operation Ability
0: disable the STE10/100 bus master ability.
1: enable the PCI bus master ability. Default value is 1 for
normal operation.
0
R/W
1
CMSA
Command Memory Space Access
0: disable the memory space access ability.
1: enable the memory space access ability.
0
R/W
Table 4. Configuration Registers Descriptions
Bit #
Name
Descriptions
Default Val
RW Type




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