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STE100P Datasheet(PDF) 16 Page - STMicroelectronics |
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STE100P Datasheet(HTML) 16 Page - STMicroelectronics |
16 / 29 page STE100P 16/29 7.2 100BASE-TX Receiving Operation Regarding the 100BASE-TX receiving operation, the device provides the receiving functions of PMD, PMA, and PCS for receiving incoming data signals through category 5 UTP cable and an isolation transformer with turns ratio of 1: 1. It includes the adaptive equalizer and baseline wander, data conversions of MLT3 to NRZI, NRZI to NRZ and serial to parallel, the PLL for clock and data recovery, the de-scrambler, and the decoder of 5B/4B. Adaptive Equalizer and Baseline Wander: Since the high speed signals over the unshielded (or shield- ed) twisted Pair cable will induce the amplitude attenuation and phase shifting. Furthermore, these effects are depends on the signal frequency, cable type, cable length and the connectors of the cabling. So a re- liable adaptive equalizer and baseline wander to compensate all the amplitude attenuation and phase shift- ing are necessary. In the transceiver, it provides the robust circuits to perform these functions. MLT3 to NRZI Decoder and PLL for Data Recovery: After receiving the proper MLT3 signals, the device converts the MLT3 to NRZI code for further processing. After adaptive equalizer, baseline wander, and MLT3 to NRZI decoder, the compensated signals with NRZI type in 125MHz are passed to the Phase Lock Loop circuits to extract out the original data and synchronous clock. Data Conversions of NRZI to NRZ and Serial to Parallel: After data is recovered, the signals will be passed to the NRZI to NRZ converter to generate the 125 MHz serial bit stream. This serial bit stream will be packed to parallel 5B type for further processing. The NRZI to NRZ conversion can be bypassed, if the bit 7 of PR19 register is cleared as 0. De-scrambling and Decoding of 5B/4B: The parallel 5B type data is passed to de-scrambler and 5B/4B decoder to return their original MII nibble type data. Carrier sensing: Carrier Sense(CRS) signal is asserted when the STE100P detects any 2 non-contiguous zeros within any 10 bit boundary of the receiving bit stream. CRS is de-asserted when ESD code-group or Idle code-group is detected. In half duplex mode, CRS is asserted during packet transmission or receive. But in full duplex mode, CRS is asserted only during packet reception. 7.3 10BASE-T Transmission Operation This includes the parallel to serial converter, Manchester Encoder, Link test function, Jabber function and the transmit wave-shaper and line driver described in the section of “Wave-Shaper and Media Signal Driver” of “100BASE-T Transmission Operation”. It also provides Collision detection and SQE test for half duplex appli- cation. 7.4 10BASE-T Receive Operation This includes the carrier sense function, receiving filter, PLL for clock and data recovering, Manchester decoder, and serial to parallel converter. 7.5 Loop-back Operation The STE100P provides internal loop-back option for both the 100BASE-TX and 10BASE-T operations. Setting bit 14 of PR0 register to 1 can enable the loop-back option. In this loop-back operation, the TX ± and RX± lines are isolated from the media. The STE100P also provides remote loop-back operation for 100BASE-TX opera- tion. Setting bit 9 of PR19 register to 1 enables the remote loop-back operation. In the 100BASE-TX internal loop-back operation, the data comes from the transmit output of NRZ to NRZI con- verter then loop-back to the receive path into the input of NRZI to NRZ converter. In the 100BASE-TX remote loop-back operation, the data is received from RX ± pins through receive path to the output of data and clock recover and then loop-back to the input of NRZI to MLT3 converter of transmit path then transmit out to the medium via the transmit line drivers. In the 10BASE-T loop-back operation, the data is through transmit path and loop-back from the output of the Manchester encoder into the input of Phase Lock Loop circuit of receive path. |
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