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CAT24C05VP2I-G3 Datasheet(PDF) 2 Page - Catalyst Semiconductor |
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CAT24C05VP2I-G3 Datasheet(HTML) 2 Page - Catalyst Semiconductor |
2 / 18 page CAT24C03/05 2 Doc. No. 1116, Rev. B © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice ABSOLUTE MAXIMUM RATINGS(1) Storage Temperature -65°C to +150°C Voltage on Any Pin with Respect to Ground(2) -0.5 V to +6.5 V RELIABILITY CHARACTERISTICS(3) Symbol Parameter Min Units NEND(4) Endurance 1,000,000 Program/ Erase Cycles TDR Data Retention 100 Years D.C. OPERATING CHARACTERISTICS VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified. Symbol Parameter Test Conditions Min Max Units ICCR Read Current Read, fSCL = 400 kHz 1 mA ICCW Write Current Write, fSCL = 400 kHz 1 mA ISB Standby Current All I/O Pins at GND or VCC 1 μA IL I/O Pin Leakage Pin at GND or VCC 1 μA VIL Input Low Voltage -0.5 VCC x 0.3 V VIH Input High Voltage VCC x 0.7 VCC + 0.5 V VOL1 Output Low Voltage VCC ≥ 2.5 V, IOL = 3.0 mA 0.4 V VOL2 Output Low Voltage VCC < 2.5 V, IOL = 1.0 mA 0.2 V PIN IMPEDANCE CHARACTERISTICS VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified. Symbol Parameter Conditions Max Units CIN(3) SDA I/O Pin Capacitance VIN = 0 V 8 pF CIN(3) Input Capacitance (other pins) VIN = 0 V 6 pF IWP(5) WP Input Current VIN < VIH, VCC = 5.5 V 200 μA VIN < VIH, VCC = 3.3 V 150 VIN < VIH, VCC = 1.8 V 100 VIN > VIH 1 Note: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this speci- fication is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. (3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Page Mode, VCC = 5 V, 25°C (5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source. |
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