List of Tables
Table 1.
Documentation Conventions ............................................................................................ 20
Table 3-1.
Memory Map ................................................................................................................... 43
Table 4-1.
Exception Types .............................................................................................................. 45
Table 4-2.
Interrupts ........................................................................................................................ 46
Table 5-1.
JTAG Port Pins Reset State ............................................................................................. 50
Table 5-2.
JTAG Instruction Register Commands ............................................................................... 55
Table 6-1.
System Control Register Map ........................................................................................... 65
Table 7-1.
Hibernation Module Register Map ................................................................................... 125
Table 8-1.
Flash Protection Policy Combinations ............................................................................. 141
Table 8-2.
Flash Resident Registers ............................................................................................... 142
Table 8-3.
Flash Register Map ........................................................................................................ 142
Table 9-1.
GPIO Pad Configuration Examples ................................................................................. 167
Table 9-2.
GPIO Interrupt Configuration Example ............................................................................ 167
Table 9-3.
GPIO Register Map ....................................................................................................... 168
Table 10-1.
Available CCP Pins ........................................................................................................ 205
Table 10-2.
16-Bit Timer With Prescaler Configurations ..................................................................... 208
Table 10-3.
Timers Register Map ...................................................................................................... 214
Table 11-1.
Watchdog Timer Register Map ........................................................................................ 241
Table 12-1.
Samples and FIFO Depth of Sequencers ........................................................................ 264
Table 12-2.
ADC Register Map ......................................................................................................... 268
Table 13-1.
UART Register Map ....................................................................................................... 302
Table 14-1.
SSI Register Map .......................................................................................................... 347
Table 15-1.
Examples of I2C Master Timer Period versus Speed Mode ............................................... 377
Table 15-2.
Inter-Integrated Circuit (I2C) Interface Register Map ......................................................... 386
Table 15-3.
Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................ 391
Table 16-1.
TX & RX FIFO Organization ........................................................................................... 413
Table 16-2.
Ethernet Register Map ................................................................................................... 416
Table 17-1.
Comparator 0 Operating Modes ...................................................................................... 454
Table 17-2.
Comparator 1 Operating Modes ..................................................................................... 455
Table 17-3.
Internal Reference Voltage and ACREFCTL Field Values ................................................. 455
Table 17-4.
Analog Comparators Register Map ................................................................................. 457
Table 18-1.
PWM Register Map ........................................................................................................ 470
Table 19-1.
QEI Register Map .......................................................................................................... 505
Table 21-1.
Signals by Pin Number ................................................................................................... 519
Table 21-2.
Signals by Signal Name ................................................................................................. 523
Table 21-3.
Signals by Function, Except for GPIO ............................................................................. 528
Table 21-4.
GPIO Pins and Alternate Functions ................................................................................. 532
Table 22-1.
Temperature Characteristics ........................................................................................... 534
Table 22-2.
Thermal Characteristics ................................................................................................. 534
Table 23-1.
Maximum Ratings .......................................................................................................... 535
Table 23-2.
Recommended DC Operating Conditions ........................................................................ 535
Table 23-3.
LDO Regulator Characteristics ....................................................................................... 536
Table 23-4.
Detailed Power Specifications ........................................................................................ 537
Table 23-5.
Flash Memory Characteristics ........................................................................................ 538
Table 23-6.
Phase Locked Loop (PLL) Characteristics ....................................................................... 538
Table 23-7.
Clock Characteristics ..................................................................................................... 538
11
November 30, 2007
Preliminary
LM3S6965 Microcontroller