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ST62T52CM-AUTO Datasheet(PDF) 42 Page - STMicroelectronics

No. de Pieza. ST62T52CM-AUTO
Descripción  8-BIT OTP/EPROM/FASTROM MCUs WITH A/D CONVERTER, SAFE RESET, AUTO-RELOAD TIMER AND EEPROM
Descarga  72 Pages
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Fabricante  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
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ST62T52CM-AUTO Datasheet(HTML) 42 Page - STMicroelectronics

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ST62T52CM-Auto ST62T62CM-Auto
TIMER (Cont’d)
A write to the TCR register will predominate over
the 8-bit counter decrement to 00h function, i.e. if a
write and a TCR register decrement to 00h occur
simultaneously, the write will take precedence,
and the TMZ bit is not set until the 8-bit counter
reaches 00h again. The values of the TCR and the
PSC registers can be read accurately at any time.
4.2.4 Timer Registers
Timer Status Control Register (TSCR)
Address: 0D4h
Read/Write
Bit 7 = TMZ: Timer Zero bit
A low-to-high transition indicates that the timer
count register has decrement to zero. This
bit
must be cleared by user software before starting a
new count.
Bit 6 = ETI: Enable Timer Interrup
When set, enables the timer interrupt request
(vector #4). If ETI=0 the timer interrupt is disabled.
If ETI=1 and TMZ=1 an interrupt request is gener-
ated.
Bit 5 = D5: Reserved
Must be set to “1”.
Bit 4 = D4
Do not care.
Bit 3 = PSI: Prescaler Initialize Bit
Used to initialize the prescaler and inhibit its count-
ing. When PSI=“0” the prescaler is set to 7Fh and
the counter is inhibited. When PSI=“1” the prescal-
er is enabled to count downwards. As long as
PSI=“0” both counter and prescaler are not run-
ning.
Bit 2, 1, 0 = PS2, PS1, PS0: Prescaler Mux. Se-
lect. These bits select the division ratio of the pres-
caler register.
Table 13. Prescaler Division Factors
Timer Counter Register (TCR)
Address: 0D3h
Read/Write
Bit 7-0 = D7-D0: Counter Bits.
Prescaler Register PSC
Address: 0D2h
Read/Write
Bit 7 = D7: Always read as "0".
Bit 6-0 = D6-D0: Prescaler Bits.
7
0
TMZ
ETI
D5
D4
PSI
PS2
PS1
PS0
PS2
PS1
PS0
Divided by
0
0
0
1
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
7
0
D7
D6
D5
D4
D3
D2
D1
D0
7
0
D7
D6
D5
D4
D3
D2
D1
D0


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