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ST62T60CB6 Datasheet(PDF) 27 Page - STMicroelectronics

No. de Pieza. ST62T60CB6
Descripción  8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, SAFE RESET, AUTO-RELOAD TIMER, EEPROM AND SPI
Descarga  84 Pages
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Fabricante  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
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ST62T60CB6 Datasheet(HTML) 27 Page - STMicroelectronics

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ST62T53C/T60C/T63C ST62E60C
3.3 DIGITAL WATCHDOG
The digital Watchdog consists of a reloadable
downcounter timer which can be used to provide
controlled recovery from software upsets.
The Watchdog circuit generates a Reset when the
downcounter reaches zero. User software can
prevent this reset by reloading the counter, and
should therefore be written so that the counter is
regularly reloaded while the user program runs
correctly. In the event of a software mishap (usual-
ly caused by externally generated interference),
the user program will no longer behave in its usual
fashion and the timer register will thus not be re-
loaded periodically. Consequently the timer will
decrement down to 00h and reset the MCU. In or-
der to maximise the effectiveness of the Watchdog
function, user software must be written with this
concept in mind.
Watchdog behaviour is governed by two options,
known
as
“WATCHDOG
ACTIVATION”
(i.e.
HARDWARE or SOFTWARE) and “EXTERNAL
STOP MODE CONTROL” (see Table 6).
In the SOFTWARE option, the Watchdog is disa-
bled until bit C of the DWDR register has been set.
When the Watchdog is disabled, low power Stop
mode is available. Once activated, the Watchdog
cannot be disabled, except by resetting the MCU.
In the HARDWARE option, the Watchdog is per-
manently enabled. Since the oscillator will run con-
tinuously, low power mode is not available. The
STOP instruction is interpreted as a WAIT instruc-
tion, and the Watchdog continues to countdown.
However, when the EXTERNAL STOP MODE
CONTROL option has been selected low power
consumption may be achieved in Stop Mode.
Execution of the STOP instruction is then gov-
erned by a secondary function associated with the
NMI pin. If a STOP instruction is encountered
when the NMI pin is low, it is interpreted as WAIT,
as described above. If, however, the STOP in-
struction is encountered when the NMI pin is high,
the Watchdog counter is frozen and the CPU en-
ters STOP mode.
When the MCU exits STOP mode (i.e. when an in-
terrupt is generated), the Watchdog resumes its
activity.
Table 6. Recommended Option Choices
Functions Required
Recommended Options
Stop Mode & Watchdog
“EXTERNAL STOP MODE” & “HARDWARE WATCHDOG”
Stop Mode
“SOFTWARE WATCHDOG”
Watchdog
“HARDWARE WATCHDOG”


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