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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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STE2007 Datasheet(PDF) 24 Page - STMicroelectronics |
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STE2007 Datasheet(HTML) 24 Page - STMicroelectronics |
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24 / 62 page  Interface STE2007 24/62 Figure 15. Bit transfer and START,STOP conditions definition Figure 16. Acknowledgment on the I2C-bus 4.3.1 Communication protocol The STE2007 is an I2C slave. The access to the device is bi-directional since data write and status read are allowed. Four are the device addresses available for the device. All have in common the first 5 bits (01111). The two least significant bit of the slave address are set by connecting the SA0 and SA1 inputs to a logic 0 or to a logic 1. 4.3.2 Starting the communication To start the communication between the bus master and the slave LCD driver, the master must initiate a START condition. Following this, the master sends an 8-bit byte, on the SDA bus line (Most significant bit first). This consists of the 7-bit Device Address Code, and the 1- bit Read/Write Designator (R/W). The R/W bit has to be set to logic 1 to logic 0 according to the type of communication (read or write). All slaves with the corresponding address acknowledge in parallel, all the others ignore the I2C-bus transfer. Figure 17. Addree byte DATA LINE STABLE DATA VALID CHANGE OF DATA ALLOWED START CONDITION STOP CONDITION CLOCK DATA D00IN1151 START CLOCK PULSE FOR ACKNOWLEDGEMENT DATA OUTPUT BY RECEIVER SCLK FROM MASTER DATA OUTPUT BY TRANSMITTER D00IN1152 1 MSB LSB 28 9 STE2007 SLAVE ADDRESS S 01111 0 A R / W S 1 A READ or WRITE DESIGNATOR ADDRESS BYTE |
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