MOTOROLA CMOS LOGIC DATA

MC14500B

308

Characteristic

Symbol

VDD

Vdc

–55

_C

25

_C

125

_C

Unit

Characteristic

Symbol

VDD

Vdc

Min

Max

Min

Typ #

Max

Min

Max

Unit

Input Current, RST

Iin

15

25

—

—

150

—

—

250

µAdc

Input Current

Iin

15

—

± 0.1

—

±0.00001

± 0.1

—

± 1.0

µAdc

Input Capacitance (Data)

Cin

—

—

—

—

15

—

—

—

pF

Input Capacitance (All Other Inputs)

Cin

—

—

—

—

5.0

7.5

—

—

pF

Quiescent Current

(Per Package) Iout = 0 µA,

Vin = 0 or VDD

IDD

5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.005

0.010

0.015

5.0

10

20

—

—

—

150

300

600

µAdc

**Total Supply Current at an

External Load Capacitance (CL)

on All Outputs

IT

—

IT = (1.5 µA/kHz) f + IDD

IT = (3.0 µA/kHz) f + IDD

IT = (4.5 µA/kHz) f + IDD

µAdc

** The formulas given are for the typical characteristics only at 25

_C.

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

CL = 130 pF + 1 TTL load for Data and Write.)

Characteristic

Symbol

VDD

Vdc

All Types

Unit

Characteristic

Symbol

VDD

Vdc

Min

Typ #

Max

Unit

Propagation Delay Time, X1 to RR

tPLH,

tPHL

5.0

10

15

—

—

—

250

125

100

500

250

200

ns

X1 to Flag F, Flag O, RTN, JMP

5.0

10

15

—

—

—

200

100

85

400

200

170

X1 to Write

5.0

10

15

—

—

—

225

125

100

450

250

200

X1 to Data

5.0

10

15

—

—

—

250

120

100

500

240

200

RST to RR

5.0

10

15

—

—

—

250

125

100

500

250

200

RST to X1

5.0

10

15

—

—

—

450

200

150

Note 1

RST to Flag F, Flag O, RTN, JMP

5.0

10

15

—

—

—

400

200

150

800

400

300

RST to Write, Data

5.0

10

15

—

—

—

450

225

175

900

450

350

Clock Pulse Width, X1

tW(cl)

5.0

10

15

400

200

180

200

100

90

—

—

—

ns

Rent Pulse Width, RST

tW(R)

5.0

10

15

500

250

200

250

125

100

—

—

—

ns

Setup Time — Instruction

tsu(l)

5.0

10

15

400

250

180

200

125

90

—

—

—

ns

Data

tsu(D)

5.0

10

15

200

100

80

100

50

40

—

—

—

Hold Time — Instruction

th(l)

5.0

10

15

100

50

50

0

0

0

—

—

—

ns

Data

th(D)

5.0

10

15

200

100

100

100

50

50

—

—

—

NOTE 1. Maximum Reset Delay may extend to one–half clock period.

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.