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ST62T10CB1 Datasheet(PDF) 85 Page - STMicroelectronics |
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ST62T10CB1 Datasheet(HTML) 85 Page - STMicroelectronics |
85 / 104 page ST6208C/ST6209C/ST6210C/ST6220C 85/104 10.9 CONTROL PIN CHARACTERISTICS 10.9.1 Asynchronous RESET Pin Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Notes: 1. Unless otherwise specified, typical data are based on TA=25°C and VDD=5V. 2. Data based on characterization results, not tested in production. 3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 4. The RON pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results, not tested in production. 5. All short pulse applied on RESET pin with a duration below th(RSTL)in can be ignored. 6. The reset network protects the device against parasitic resets, especially in a noisy environment. 7. The output of the external reset circuit must have an open-drain output to drive the ST6 reset pad. Otherwise the device can be damaged when the ST6 generates an internal reset (LVD or watchdog). Figure 69. Typical RON vs VDD with VIN=VSS Symbol Parameter Conditions Min Typ 1) Max Unit VIL Input low level voltage 2) 0.3xVDD V VIH Input high level voltage 2) 0.7xVDD Vhys Schmitt trigger voltage hysteresis 3) 200 400 mV RON Weak pull-up equivalent resistor 4) VIN=VSS VDD=5V 150 350 900 k Ω VDD=3.3V 300 730 1900 RESD ESD resistor protection VIN=VSS VDD=5V 2.8 k Ω VDD=3.3V tw(RSTL)out Generated reset pulse duration External pin or internal reset sources tCPU µs th(RSTL)in External reset pulse hold time 5) µs tg(RSTL)in Filtered glitch duration 6) ns 34 56 VDD [V] 100 200 300 400 500 600 700 800 900 1000 Ron [Kohm] Ta=-40°C Ta=25°C Ta=95°C Ta=125°C 1 |
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