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ADS8318IBDGST Datasheet(PDF) 5 Page - Texas Instruments |
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ADS8318IBDGST Datasheet(HTML) 5 Page - Texas Instruments |
5 / 28 page TIMING REQUIREMENTS ADS8318 www.ti.com ........................................................................................................................................................................................................ SLAS568 – MAY 2008 All specifications typical at –40 °C to 85°C, +VA = 5 V, +VBD ≥ 4.5 V PARAMETER REF FIGURE MIN TYP MAX UNIT SAMPLING AND CONVERSION RELATED tacq Acquisition time 600 ns Figure 46, Figure 48, Figure 50, tcnv Conversion time 1400 ns Figure 52 tcyc Time between conversions 2000 ns t1 Pulse duration, CONVST high Figure 46, Figure 48 10 ns t6 Pulse duration, CONVST low Figure 50, Figure 52, Figure 54 20 ns I/O RELATED tclk SCLK Period 20 ns tclkl SCLK Low time 9 ns Figure 46, Figure 48, Figure 50, tclkh SCLK High time 9 ns Figure 52, Figure 54, Figure 56 t2 SCLK Falling edge to data remains valid 5 ns t3 SCLK Falling edge to next data valid delay 16 ns ten Enable time, CONVST or SDI Low to MSB valid Figure 46, Figure 50 15 ns Disable time, CONVST or SDI high or last SCLK falling edge Figure 46, Figure 48, Figure 50, tdis 12 ns to SDO 3-state (CS mode) Figure 52 t4 Setup time, SDI valid to CONVST rising edge 5 ns Figure 50, Figure 52 t5 Hold time, SDI valid from CONVST rising edge 5 ns t7 Setup time, SCLK valid to CONVST rising edge 5 ns Figure 54 t8 Hold time, SCLK valid from CONVST rising edge 5 ns Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): ADS8318 |
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