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ADS6149IRGZT Datasheet(PDF) 10 Page - Texas Instruments |
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ADS6149IRGZT Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 68 page  TIMING REQUIREMENTS – LVDS AND CMOS MODES (1) ADS6149/ADS6129 ADS6148/ADS6128 SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com Typical values are at 25°C, AVDD = 3.3V, DRVDD = 1.8V, sampling frequency = 250 MSPS, sine wave input clock, CLOAD = 5pF (2), R LOAD = 100Ω (3), LOW SPEED mode disabled, unless otherwise noted. Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3V, DRVDD = 1.7V to 1.9V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT The delay in time between the rising edge of the input sampling clock and ta Aperture delay 0.7 1.2 1.7 ns the actual time at which the sampling occurs tj Aperture jitter 170 fs rms Time to valid data after coming out of STANDBY mode 0.3 1 µs Time to valid data after coming out of PDN GLOBAL mode 25 100 Wake-up time clock Time to valid data after stopping and restarting the input clock 10 cycles clock ADC Latency(4) Default, after reset 18 cycles DDR LVDS MODE (5) tsu Data setup time Data valid (6) to zero-crossing of CLKOUTP 0.8 1.2 ns th Data hold time Zero-crossing of CLKOUT to data becoming invalid(6) 0.25 0.6 ns tPDI Clock propagation delay Input clock rising edge cross-over to output clock rising edge cross-over 0.2 × ts + tdelay ns 100 MSPS ≤ Sampling frequency ≤ 250 MSPS tdelay 5.0 6.2 7.5 ns Duty cycle of differential clock, (CLKOUTP–CLKOUTM) LVDS bit clock duty cycle 52% 100 MSPS ≤ Sampling frequency ≤ 250 MSPS Rise time measured from –100 mV to 100 mV tRISE, Data rise time, Fall time measured from 100 mV to –100 mV 0.08 0.14 0.2 ns tFALL Data fall time 1 MSPS ≤ Sampling frequency ≤ 250 MSPS Rise time measured from –100 mV to 100 mV tCLKRISE, Output clock rise time, Fall time measured from 100 mV to –100 mV 0.08 0.14 0.2 ns tCLKFALL Output clock fall time 1 MSPS ≤ Sampling frequency ≤ 250 MSPS tOE Output enable (OE) to data delay Time to valid data after OE becomes active 40 ns PARALLEL CMOS MODE(7) tSTART Input clock to data delay Input clock rising edge cross-over to start of data valid(8) 3.2 ns tDV Data valid time Time interval of valid data(8) 0.7 1.5 ns tPDI Clock propagation delay Input clock rising edge cross-over to output clock rising edge cross-over 0.78 × ts + tdelay 100 MSPS ≤ Sampling frequency ≤ 150 MSPS tdelay 5 6.5 8 ns Duty cycle of differential clock, (CLKOUT) Output clock duty cycle 50% 100 MSPS ≤ Sampling frequency ≤ 150 MSPS tRISE, Data rise time, Rise time measured from 20% to 80% of DRVDD, Fall time measured from 80% to 20% of DRVDD, 0.7 1.2 2 ns tFALL Data fall time 1 MSPS ≤ Sampling frequency ≤ 250 MSPS Rise time measured from 20% to 80% of DRVDD, tCLKRISE, Output clock rise time, Fall time measured from 80% to 20% of DRVDD, 0.5 1 1.5 ns tCLKFALL Output clock fall time 1 MSPS ≤ Sampling frequency ≤ 150 MSPS tOE Output enable (OE) to data delay Time to valid data after OE becomes active 20 ns (1) Timing parameters are specified by design and characterization and not tested in production. (2) CLOAD is the effective external single-ended load capacitance between each output pin and ground (3) RLOAD is the differential load resistance between the LVDS output pair. (4) At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1. (5) Measurements are done with a transmission line of 100 Ω characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. (6) Data valid refers to LOGIC HIGH of +100mV and LOGIC LOW of –100mV. (7) For Fs> 150 MSPS, it is recommended to use external clock for data capture and NOT the device output clock signal (CLKOUT). (8) Data valid refers to LOGIC HIGH of 1.26V and LOGIC LOW of 0.54V. 10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128 |
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