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HCPL2601W Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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HCPL2601W Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 12 page ©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com 6N137, HCPL2601, HCPL2611, HCPL2630, HCPL2631 Rev. 1.0.7 August 2008 Single-Channel: 6N137, HCPL2601, HCPL2611 Dual-Channel: HCPL2630, HCPL2631 High Speed 10MBit/s Logic Gate Optocouplers Features ■ Very high speed – 10 MBit/s ■ Superior CMR – 10 kV/µs ■ Double working voltage-480V ■ Fan-out of 8 over -40°C to +85°C ■ Logic gate output ■ Strobable output ■ Wired OR-open collector ■ U.L. recognized (File # E90700) Applications ■ Ground loop elimination ■ LSTTL to TTL, LSTTL or 5-volt CMOS ■ Line receiver, data transmission ■ Data multiplexing ■ Switching power supplies ■ Pulse transformer replacement ■ Computer-peripheral interface Description The 6N137, HCPL2601, HCPL2611 single-channel and HCPL2630, HCPL2631 dual-channel optocouplers consist of a 850 nm AlGaAS LED, optically coupled to a very high speed integrated photo-detector logic gate with a strobable output. This output features an open collec- tor, thereby permitting wired OR outputs. The coupled parameters are guaranteed over the temperature range of -40°C to +85°C. A maximum input signal of 5mA will provide a minimum output sink current of 13mA (fan out of 8). An internal noise shield provides superior common mode rejection of typically 10kV/µs. The HCPL2601 and HCPL2631 has a minimum CMR of 5kV/µs. The HCPL2611 has a minimum CMR of 10kV/µs. Schematics Package Outlines 8 1 8 1 8 1 A 0.1µF bypass capacitor must be connected between pins 8 and 5(1). 1 2 3 4 5 6 7 8 N/C _ V CC V E V O GND + N/C V F 1 2 3 4 5 6 7 8 + _ V F1 V CC V 01 V 02 GND V F2 _ + HCPL2630 HCPL2631 6N137 HCPL2601 HCPL2611 Truth Table (Positive Logic) Input Enable Output H H L L H H H L H L L H H NC L L NC H |
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