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STS1HNC60 Datasheet(PDF) 1 Page - STMicroelectronics |
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STS1HNC60 Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 6 page  1/6 PRELIMINARY DATA July 2001 STS1HNC60 N-CHANNEL 600V - 7 Ω - 0.4A SO-8 PowerMesh™II MOSFET s TYPICAL RDS(on) = 7 Ω s EXTREMELY HIGH dv/dt CAPABILITY s 100% AVALANCHE TESTED s NEW HIGH VOLTAGE BENCHMARK s GATE CHARGE MINIMIZED DESCRIPTION Using the latest high voltage MESH OVERLAY™II process, STMicroelectronics has designed an ad- vanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprietary edge termi- nation structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and switching characteris- tics. APPLICATIONS s SWITCH MODE LOW POWER SUPPIES (SMPS) s CFL ABSOLUTE MAXIMUM RATINGS (•)Pulse width limited by safe operating area TYPE VDSS RDS(on) ID STS1HNC60 600 V < 8 Ω 0.36 A Symbol Parameter Value Unit VDS Drain-source Voltage (VGS = 0) 600 V VDGR Drain-gate Voltage (RGS = 20 kΩ) 600 V VGS Gate- source Voltage ± 30 V ID Drain Current (continuos) at TC = 25°C 0.36 A ID Drain Current (continuos) at TC = 100°C 0.22 A IDM (q) Drain Current (pulsed) 1.44 A PTOT Total Dissipation at TC = 25°C 2.5 W Derating Factor 0.028 W/°C dv/dt(1) Peak Diode Recovery voltage slope 3.5 V/ns Tstg Storage Temperature –65 to 150 °C Tj Max. Operating Junction Temperature 150 °C (1)ISD ≤ 0.36 A, di/dt ≤100A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX. SO-8 INTERNAL SCHEMATIC DIAGRAM |
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