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ADS1282 Datasheet(PDF) 3 Page - Texas Instruments |
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ADS1282 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 52 page  ELECTRICAL CHARACTERISTICS ADS1282 www.ti.com ........................................................................................................................................ SBAS418E – SEPTEMBER 2007 – REVISED OCTOBER 2008 Limit specifications at –40°C to +85°C. Typical specifications at +25°C, AVDD = +2.5V, AVSS = –2.5V, fCLK (1) = 4.096MHz, VREFP = +2.5V, VREFN = –2.5V, DVDD = +3.3V, CAPN – CAPP = 10nF, PGA = 1, High-Resolution Mode, and fDATA = 1000SPS, unless otherwise noted. ADS1282 PARAMETER CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS Full-scale input voltage VIN = (AINP – AINN) ±VREF/2 × PGA V Absolute input range AINP or AINN AVSS + 0.7 AVDD – 1.25 V PGA input voltage noise density 5 nV/ √Hz Differential input impedance(2) 1 G Ω Common-mode input impedance 100 M Ω Input bias current 1 nA Crosstalk f = 31.25Hz –135 dB MUX on-resistance 30 Ω PGA OUTPUT (CAPP, CAPN) Absolute output range AVSS + 0.4 AVDD – 0.4 V PGA differential output impedance 600 Ω Output impedance tolerance ±10 % External bypass capacitance 10 100 nF High-resolution mode 55 k Ω Modulator differential input impedance Low-power mode 110 k Ω AC PERFORMANCE High-resolution mode 120 124 Signal-to-noise ratio(3) SNR dB Low-power mode 117 121 High-resolution mode PGA = 1...16 –122 –114 PGA = 32 –117 –110 dB PGA = 64 –115 Total harmonic distortion(4) THD Low-power mode PGA = 1...16 –122 –114 PGA = 32 –113 –108 dB PGA = 64 –109 Spurious-free dynamic dB SFDR 123 range DC PERFORMANCE Resolution No missing codes 31 Bits FIR filter mode 250 4000 SPS Data rate fDATA Sinc filter mode 8000 128,000 SPS Integral nonlinearity (INL)(5) Differential input 0.00005 0.0004 % FSR(6) Offset error 50 200 µV Offset error after calibration(7) Shorted input 1 µV Offset drift 0.02 µV/°C High-resolution mode –1.5 –1.0 –0.5 % Gain error(8) Low-power mode –1 –0.5 0 % Gain error after calibration(7) 0.0002 % (1) fCLK = system clock. (2) Input impedance is improved by disabling input chopping (CHOP bit = 0). (3) VIN = 20mVDC/PGA, see Table 1. (4) VIN = 31.25Hz, –0.5dBFS. (5) Best-fit method. (6) FSR: Full-scale range = ±VREF/2 × PGA. (7) Calibration accuracy is on the level of noise reduced by 4 (calibration averages 16 readings). (8) The PGA output impedance and the modulator input impedance results in –1% systematic gain error (high-resolution mode) and –0.5% error (low-power mode). Copyright © 2007–2008, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): ADS1282 |
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