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74FCT162652CTPVCT Datasheet(PDF) 1 Page - Texas Instruments |
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74FCT162652CTPVCT Datasheet(HTML) 1 Page - Texas Instruments |
1 / 16 page 16-Bit Registered Transceivers CY74FCT16652T CY74FCT162652T Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. SCCS061B - July 1994 - Revised September 2001 Copyright © 2001, Texas Instruments Incorporated 1CY74FCT162652T Features •Ioff supports partial-power-down mode operation • Edge-rate control circuitry for significantly improved noise characteristics • Typical output skew < 250 ps • ESD > 2000V • TSSOP (19.6-mil pitch) and SSOP (25-mil pitch) packages • Industrial temperature range of −40˚C to +85˚C •VCC = 5V ± 10% CY74FCT16652T Features: • 64 mA sink current, 32 mA source current • Typical VOLP (ground bounce) <1.0V at VCC = 5V, TA = 25˚C CY74FCT162652T Features: • Balanced 24 mA output drivers • Reduced system switching noise • Typical VOLP (ground bounce) <0.6V at VCC = 5V, TA= 25˚C Functional Description These 16-bit, high-speed, low-power, registered transceivers that are organized as two independent 8-bit bus transceivers with three-state D-type registers and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal storage registers. OEAB and OEBA control pins are provided to control the transceiver functions. SAB and SBA control pins are provided to select either real-time or stored data transfer. Data on the A or B data bus, or both, can be stored in the internal D flip-flops by LOW-to-HIGH transitions at the appropriate clock pins (CLKAB or CLKBA), regardless of the select or enable control pins. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16652T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162652T has 24-mA balanced output drivers with current-limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162652T is ideal for driving transmission lines. TO 7 OTHER CHANNELS 1OEAB C D 1A1 1OEBA 1CLKBA 1CLKAB 1SBA B REG C D A REG 1B1 1SAB FCT16652-1 2OEAB 2SAB 2OEBA 2CLKBA 2CLKAB 2SBA 2B1 2A1 C D B REG C D A REG TO 7 OTHER CHANNELS FCT16652-2 Logic Block Diagrams |
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