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TDA7326 Datasheet(PDF) 5 Page - STMicroelectronics |
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TDA7326 Datasheet(HTML) 5 Page - STMicroelectronics |
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5 / 16 page  2.0 GENERAL DESCRIPTION This circuit contains a frequency synthesizer and a loop filter for an FM and AM radio tuning sys- tem. Only a VCO is required to build a complete PLL system. For FM and SW application, the counter works in a two stages configuration. The first stage is a swallow counter with a four modulus (:32/33/64/65) precounter. The second stage is an 8-bit programmable counter. For LW and MW application, a 14-bit programma- ble counter is available. The circuit receives the scaling factors for the pro- grammable counters and the values of the refer- ence frequencies via a three line serial bus inter- face. The reference frequency is generated by a 4MHz XTAL oscillator followed by the reference divider. An external oscillator (f = 4MHz) can be used in- stead of the internal one; it must be connected to OSCIN (pin 7). The reference step-frequency is 1 or 2.5kHz for AM. For FM mode a step frequency of 12.5 and 25kHz can be selected. The circuit checks the format of the received data words. Valid data in the interface shift register are stored automatically in buffer registers at the end of transmission. The output signals of the phase detector are switching the programmable current sources. Their currents are integrated in the loop filter to a DC voltage.The values of the current sources are programmable by two bits also received via the serial bus. The loop filter amplifier is supplied by a separate positive power supply, to minimize the noise in- duced by the digital part of the system. The loop gain can be set for different conditions. After a power on reset, all registers are reset to zero and the standby mode is activated. In standby mode, oscillator, reference counter, AM input and FM input are stopped. The power consumption is reduced to a minimum. 3.0 DETAILED DESCRIPTION OF THE PLL FREQUENCY SYNTHESIZER 3.1 INPUT AMPLIFIERS The signals applied on AM and FM input are am- plified to get a logic level in order to drive the fre- quency dividers. 3.1.1 Input Impedance The typical input impedance: for the FM input is 200 Ω and for AM input is 1.4kΩ. 3.1.2 Input sensitivity (see Figures 1a and 1b). 3.2 DATA AND CONTROL REGISTER 3.2.1 Register Location The data registers (bit2...bit7) for the control register and the data registers PC7...PC0, SC5...SC0 for the counters are organized in four words, identified by two address bits (bit 7 and bit 6), bit 7 is the first bit to be sent by the controller, bit0 is the last one. The order and the number of the bytes to be transmitted is free of choice. The modification of the PC7...PC0 registers is valid for the internal counters only after transmission of byte 4 (SC5...SC0). ADDRESS BITS DATA BITS BYTE MSB-BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 Function adr 0 adr 1 data 0 data 1 data 2 data 3 data 4 data 5 byte 1 0 0 test 0 test 1 test 2 SOUT CURR2 fREF byte 2 0 1 PC7 PC6 LPF1/2 CURR 1 SWM/DIR AM/FM byte 3 1 0 PC5 PC4 PC3 PC2 PC1 PC0 byte 4 1 1 SC5 SC4 SC3 SC2 SC1 SC0 3.2.2 CONTROL AND STATUS REGISTERS Register Configuration REGISTER NAME FUNCTION SWM/DIR Swallow direct-mode switch 1 = SWM, 0 = DIR AM/FM AM - FM band switch 1=AM, 0 = FM fREF Selection of reference frequency (see table 3.4) CURR1 Current select of change pump CURR2 Current select of change pump LPF1/LPF2 Loop filter input select 1= IPF1,0 = IPF2 SOUT Switch output condition 1=output high, 0 = output low TDA7326 5/16 |
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