MC54/74HC4066A

MOTOROLA

High–Speed CMOS Logic Data

DL129 — Rev 6

4

Symbol

Parameter

Test Conditions

VCC

V

Limit*

25

_C

54/74HC

Unit

BW

Maximum On–Channel Bandwidth or

Minimum Frequency Response

(Figure 5)

fin = 1 MHz Sine Wave

Adjust fin Voltage to Obtain 0 dBm at VOS

Increase fin Frequency Until dB Meter Reads – 3 dB

RL = 50 Ω, CL = 10 pF

4.5

9.0

12.0

150

160

160

MHz

—

Off–Channel Feedthrough Isolation

(Figure 6)

fin  Sine Wave

Adjust fin Voltage to Obtain 0 dBm at VIS

fin = 10 kHz, RL = 600 Ω, CL = 50 pF

4.5

9.0

12.0

– 50

– 50

– 50

dB

fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF

4.5

9.0

12.0

– 40

– 40

– 40

—

Feedthrough Noise, Control to

Switch

(Figure 7)

Vin v 1 MHz Square Wave (tr = tf = 6 ns)

Adjust RL at Setup so that IS = 0 A

RL = 600 Ω, CL = 50 pF

4.5

9.0

12.0

60

130

200

mVPP

RL = 10 kΩ, CL = 10 pF

4.5

9.0

12.0

30

65

100

—

Crosstalk Between Any Two Switches

(Figure 12)

fin  Sine Wave

Adjust fin Voltage to Obtain 0 dBm at VIS

fin = 10 kHz, RL = 600 Ω, CL = 50 pF

4.5

9.0

12.0

– 70

– 70

– 70

dB

fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF

4.5

9.0

12.0

– 80

– 80

– 80

THD

Total Harmonic Distortion

(Figure 14)

fin = 1 kHz, RL = 10 kΩ, CL = 50 pF

THD = THDMeasured – THDSource

VIS = 4.0 VPP sine wave

VIS = 8.0 VPP sine wave

VIS = 11.0 VPP sine wave

4.5

9.0

12.0

0.10

0.06

0.04

%

* Guaranteed limits not tested. Determined by design and verified by qualification.