ABSOLUTE MAXIMUM RATINGS

(1)

PACKAGE THERMAL DATA

(1)

TPS7A45xx

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PRODUCT

xx is nominal output voltage

15 = 1.5 V (ACTIVE), 18 = 1.8 V (ACTIVE), 25 = 2.5 V (ACTIVE),

TPS7A45xxyyyz

33 = 3.3 V (ACTIVE), 01 = adjustable (ACTIVE)

yyy is package designator (KTT)

z is package quantity (R = 500)

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2)

Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

over operating virtual-junction temperature range (unless otherwise noted)

IN

–20 V to 20 V

OUT

–20 V to 20 V

–20 V to 20 V

SENSE

–20 V to 20 V

ADJ

–7 V to 7 V

SHDN

–20 V to 20 V

Indefinite

300°C

–40°C to 125°C

–65°C to 150°C

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

Absolute maximum input-to-output differential voltage cannot be achieved with all combinations of rated IN pin and OUT pin voltages.

With the IN pin at 20 V, the OUT pin may not be pulled below 0 V. The total measured voltage from IN to OUT can not exceed ±20 V.

PACKAGE

BOARD

θ

JA

θ

JC

θ

JP

(2)

TO-263 (KTT)

High K, JESD 51-5

26.5°C/W

31.8°C/W

0.38°C/W

(1)

(2)

For packages with exposed thermal pads, such as QFN, PowerPAD™, and PowerFLEX™,

θ

between the die junction and the bottom of the exposed pad.

2

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