ADS6128IRGZRG4 datasheet(9/70 Pages) TI

No. de pieza	ADS6128IRGZRG4

Descripción Electrónicos	14/12-Bit, 250/210 MSPS ADCs With DDR LVDS and Parallel CMOS Outputs

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Fabricante Electrónico	TI [Texas Instruments]

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DIGITAL CHARACTERISTICS – ADS614x and ADS612x

Dn_Dn+1_P

Dn_Dn+1_M

GND

V

OCM

V

OCM

Logic0

V

= –350mV

ODL

(1)

Logic1

V

=350mV

ODH

(1)

T0399-01

ADS6149/ADS6129

ADS6148/ADS6128

www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008

The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic

level 0 or 1. AVDD = 3.3 V, DRVDD = 1.8 V

ADS6149/ADS6148/

ADS6129/ADS6128

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

DIGITAL INPUTS – RESET, SCLK, SDATA, SEN(1)

High-level input voltage

1.3

V

All digital inputs support 1.8V and 3.3V CMOS logic

levels

Low-level input voltage

0.4

V

SDATA, SCLK(2)

VHIGH = 3.3V

16

High-level input current

µA

SEN(3)

VHIGH = 3.3V

10

SDATA, SCLK

VLOW = 0V

0

Low-level input current

µA

SEN

VLOW = 0V

–20

Input capacitance

4

pF

DIGITAL OUTPUTS – CMOS INTERFACE (Pins D0 to D13 and OVR_SDOUT)

High-level output voltage

DRVDD

V

Low-level output voltage

0

V

Output capacitance (internal to device)

2

pF

DIGITAL OUTPUTS – LVDS INTERFACE (Pins D0_D1_P/M to D12_D13_P/M)(4)

VODH, High-level output voltage

(5)

275

350

425

mV

VODL, Low-level output voltage

(5)

–425

–350

–275

mV

VOCM, Output common-mode voltage

1

1.2

1.3

V

Capacitance inside the device, from either output to

Output capacitance

2

pF

ground

(1)

SCLK, SDATA, SEN function as digital input pins in serial configuration mode.

(2)

SDATA, SCLK have internal 200 k

Ω pull-down resistor

(3)

SEN has internal 100 k

Ω pull-up resistor to AVDD. Since the pull-up is weak, SEN can also be driven by 1.8V or 3.3V CMOS buffers.

(4)

OVR_SDOUT has CMOS output logic levels, determined by DRVDD voltage.

(5)

With external 100

Ω termination

Figure 1. LVDS Voltage Levels

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Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128

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ADS6128IRGZRG4 Datasheet(PDF) 9 Page - Texas Instruments

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